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    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
    11.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250046663A1

    公开(公告)日：2025-02-06

    申请号：US18667258

    申请日：2024-05-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejun JEON ,  Yongkwan LEE ,  Seunghwan KIM ,  Junwoo PARK ,  Gyuhyeong KIM

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/64

    Abstract: A semiconductor package includes a package substrate having a first region, a second region and third region sequentially arranged from a first side portion to a second side portion thereof. The second region has a chip mounting region in a central region. A semiconductor chip is disposed in the chip mounting region and is mounted on a plurality of substrate pads of the package substrate. A pair of first flow control structures is disposed in the first region and is arranged symmetrically on both sides along a center line passing through a center of the chip mounting region. At least one pair of second flow control structures is disposed in the second region of the package substrate and is arranged symmetrically on both sides of the chip mounting region. A molding member is on the package substrate and fills a gap between the semiconductor chip and the package substrate.

    SEMICONDUCTOR MOLDING APPARATUS AND COMPRESSION MOLDING METHOD USING THE SAME
    12.
    发明申请
    SEMICONDUCTOR MOLDING APPARATUS AND COMPRESSION MOLDING METHOD USING THE SAME 有权

    公开(公告)号：US20240420972A1

    公开(公告)日：2024-12-19

    申请号：US18402567

    申请日：2024-01-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK

    IPC: H01L21/67 ,  H01L21/56

    Abstract: Disclosed are semiconductor molding apparatuses and compression molding methods. The semiconductor molding apparatus comprises an upper mold capable of supporting a substrate, a lower mold that provides a first cavity capable of being filled with a resin, a guide member that provides a second cavity to be filled with the resin and vertically penetrates the lower mold, and a guide lift capable of driving the guide member to vertically move. The lower mold includes a base plate that extends in a horizontal direction and a sidewall member that upwardly extends from the base plate. The guide lift drives the guide member to vertically move such that a top surface of the guide member moves between a top surface of the base plate and a top surface of the sidewall member.

    SEMICONDUCTOR PACKAGE
    14.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220068904A1

    公开(公告)日：2022-03-03

    申请号：US17220468

    申请日：2021-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongho PARK ,  Seung Hwan KIM ,  Jun Young OH ,  Jungjoo KIM ,  Yongkwan LEE ,  Dong-Ju JANG

    IPC: H01L25/18 ,  H01L23/538 ,  H01L25/00

    Abstract: A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.

    SEMICONDUCTOR PACKAGE
    15.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210375831A1

    公开(公告)日：2021-12-02

    申请号：US17399233

    申请日：2021-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongho PARK ,  Kyungsuk OH ,  Hyunki KIM ,  Yongkwan LEE ,  Sangsoo KIM ,  Seungkon MOK ,  Junyoung OH ,  Changyoung YOO

    IPC: H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

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