公开(公告)号：US20220068904A1

公开(公告)日：2022-03-03

申请号：US17220468

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Seung Hwan KIM ,  Jun Young OH ,  Jungjoo KIM ,  Yongkwan LEE ,  Dong-Ju JANG

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/00

Abstract: A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.