公开(公告)号：US09552252B2

公开(公告)日：2017-01-24

申请号：US14467983

申请日：2014-08-25

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Brian T. Edgar ,  Mark Gaertner ,  Bruce Buch

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1012 ,  H03M13/09 ,  H03M13/096

Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

Abstract translation: 本公开的某些示例性方面涉及其中逻辑电路基于从主机接收的用户数据生成错误检测码的方法和装置，并进一步产生要写入非易失性存储器的第一组校验位 通过将错误检测码与用户数据的散列数据地址组合在一起，与用户数据相结合。 在一些实施例中，与用户数据相关联的校验位提供用户数据被写入非易失性存储器电路的适当物理块地址中的验证。