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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160126888A1

    公开(公告)日：2016-05-05

    申请号：US14925161

    申请日：2015-10-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

    IPC: H03B5/12 ,  H03L7/099

    CPC classification number: H03L7/099 ,  H01L27/1156 ,  H03K3/0315

    Abstract: An object of the present invention is to provide a semiconductor device including an oscillator circuit including a circuit between inverters. In the circuit, a sum of the length (a1) of a wiring path between a terminal A and a terminal C1 and a length (b1) of a wiring path between a terminal D1 and a terminal B is substantially equal to a sum of the length (a2) of a wiring path between the terminal A and a terminal C2 and the length (b2) of a wiring path between a terminal D2 and the terminal B.

    Abstract translation: 本发明的目的是提供一种包括在逆变器之间包括电路的振荡器电路的半导体器件。 在该电路中，端子A和端子C1之间的布线路径的长度（a1）和端子D1与端子B之间的布线路径的长度（b1）之和基本上等于 端子A和端子C2之间的布线路径的长度（a2）和端子D2与端子B之间的布线路径的长度（b2）。

    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150256181A1

    公开(公告)日：2015-09-10

    申请号：US14635115

    申请日：2015-03-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

    IPC: H03K19/177

    CPC classification number: H03K19/1776

    Abstract: To provide a semiconductor device in which signal-transmission speed between a first logic element and a second logic element is not lowered. The semiconductor device includes a first switch between the first logic element and the second logic element, and configuration to the first switch is repeatedly performed until configuration is performed on the first switch while a low-level voltage is input to the first switch from the first logic element.

    Abstract translation: 提供一种半导体器件，其中第一逻辑元件与第二逻辑元件之间的信号传输速度不降低。 半导体器件包括第一逻辑元件和第二逻辑元件之间的第一开关，并且重复执行到第一开关的配置，直到在第一开关上执行配置，同时从第一开关向第一开关输入低电平电压 逻辑元素。

    METHOD FOR DRIVING SEMICONDUCTOR DEVICE
    13.
    发明申请
    METHOD FOR DRIVING SEMICONDUCTOR DEVICE 有权
    驱动半导体器件的方法

    公开(公告)号：US20150256161A1

    公开(公告)日：2015-09-10

    申请号：US14636529

    申请日：2015-03-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

    IPC: H03K3/356 ,  H03K3/012 ,  H01L29/786 ,  H03K17/0412 ,  H03K17/687

    CPC classification number: H03L7/0995 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78693 ,  H03K3/0315 ,  H03K3/356086 ,  H03K5/131 ,  H03K5/26 ,  H03K17/04123 ,  H03K17/687 ,  H03L7/093 ,  H03L7/099

    Abstract: A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverter. A second terminal of each of the first and second circuits is electrically connected to an input terminal of the (i+1)-th inverter. The first circuit has functions of storing first data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the first data. The second circuit has functions of storing second data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the second data.

    Abstract translation: 提供了一种新的PLL。 振荡电路包括第一至第n反相器以及第一和第二电路。 第一和第二电路中的每一个的第一端子电连接到第i个逆变器的输出端子。 第一和第二电路中的每一个的第二端子电连接到第（i + 1）个逆变器的输入端子。 第一电路具有存储第一数据的功能，在第一终端与第二终端电断开之间进行切换，并且将第一终端与第二终端之间的电阻设置为基于第一数据的值。 第二电路具有存储第二数据的功能，在第一端子和第二端子彼此电断开之间切换，并且将第一端子和第二端子之间的电阻设置为基于第二数据的值。

    MEMORY DEVICE
    14.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20250072009A1

    公开(公告)日：2025-02-27

    申请号：US18947085

    申请日：2024-11-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO ,  Hiromichi GODO ,  Kazuki TSUDA ,  Hitoshi KUNITAKE

    IPC: H10B63/00

    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

    ELECTRONIC DEVICE
    15.
    发明申请
    ELECTRONIC DEVICE 有权

    公开(公告)号：US20250037654A1

    公开(公告)日：2025-01-30

    申请号：US18697595

    申请日：2022-09-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

    IPC: G09G3/3233 ,  G06F3/01 ,  G06F3/041 ,  G09G3/32

    Abstract: A novel electronic device is provided. The electronic device includes a display apparatus, an arithmetic portion, and a gaze detection portion, and the display apparatus includes a functional circuit and a display portion divided into a plurality of sub-display portions. The gaze detection portion has a function of detecting a gaze of a user. The arithmetic portion has a function of distributing each of the plurality of sub-display portions into a first section or a second section on the basis of a detection result by the gaze detection portion. The first section includes a region overlapping with a gaze point. The functional circuit has a function of making the driving frequency of the second section lower than the driving frequency of the first section. The functional circuit also has a function of making a resolution of an image displayed on the sub-display portions included in the second section lower than a resolution of an image displayed on the sub-display portions included in the first section.

    SEMICONDUCTOR DEVICE
    16.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240251567A1

    公开(公告)日：2024-07-25

    申请号：US18561961

    申请日：2022-05-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO

    IPC: H10B61/00 ,  G11C5/06 ,  H10N50/10 ,  H10N50/80

    CPC classification number: H10B61/22 ,  G11C5/063 ,  H10N50/10 ,  H10N50/80

    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer. The first element layer includes a first memory cell, a first electrode, a second electrode, and a third electrode. The first memory cell includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The first electrode is electrically connected to the third electrode via the second electrode. The third electrode is provided to be exposed on a surface of the first element layer. The first through electrode is provided to be exposed on a surface of the second substrate and is electrically connected to the first electrode. The second substrate and the first element layer are provided to be stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The first transistor is provided in a region overlapping with the first through electrode.

    MEMORY DEVICE
    18.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147687A1

    公开(公告)日：2024-05-02

    申请号：US18382075

    申请日：2023-10-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Hiroki INOUE ,  Yuki OKAMOTO

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.

    SEMICONDUCTOR DEVICE AND OPERATION METHOD OF SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE AND OPERATION METHOD OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220172766A1

    公开(公告)日：2022-06-02

    申请号：US17602431

    申请日：2020-04-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Toshiki HAMADA

    IPC: G11C11/405 ,  G11C11/4091 ,  G11C11/56 ,  H01L29/786

    Abstract: A semiconductor device storing data as a multilevel potential is provided. The semiconductor device includes a memory cell, first and second reference cells, first and second sense amplifiers, and first to third circuits. The first circuit has a function of outputting, to a first wiring and a third wiring, a first potential corresponding to a first signal output from the memory cell. The second circuit has a function of outputting, to a second wiring, a first reference potential corresponding to a second signal output from the first reference cell. The third circuit has a function of outputting, to the fourth wiring, a second reference potential corresponding to a third signal output from the second reference cell when a second switch is in an off state. The first sense amplifier refers to the first potential and the first reference potential and changes potentials of the first wiring and the second wiring. The second sense amplifier refers to the first potential and the second reference potential and changes potentials of the third wiring and the fourth wiring.

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