公开(公告)号：US20160190387A1

公开(公告)日：2016-06-30

申请号：US14983624

申请日：2015-12-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Wenhong Sun ,  Alexander Dobrinsky ,  Maxim S. Shatalov ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/14 ,  H01L33/06

CPC classification number: H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/12

Abstract: A solution for fabricating a group III nitride heterostructure and/or a corresponding device is provided. The heterostructure can include a nucleation layer, which can be grown on a lattice mismatched substrate using a set of nucleation layer growth parameters. An aluminum nitride layer can be grown on the nucleation layer using a set of aluminum nitride layer growth parameters. The respective growth parameters can be configured to result in a target type and level of strain in the aluminum nitride layer that is conducive for growth of additional heterostructure layers resulting in strains and strain energies not exceeding threshold values which can cause relaxation and/or dislocation formation.

Abstract translation: 提供了用于制造III族氮化物异质结构和/或相应器件的解决方案。 异质结构可以包括成核层，其可以使用一组成核层生长参数在晶格失配的衬底上生长。 可以使用一套氮化铝层生长参数在成核层上生长氮化铝层。 可以将各自的生长参数配置为导致氮化铝层中的目标类型和应变水平，其有助于附加异质结构层的生长，导致应变和应变能不超过可引起松弛和/或位错形成的阈值 。

公开(公告)号：US20160035936A1

公开(公告)日：2016-02-04

申请号：US14822508

申请日：2015-08-10

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L33/18 ,  H01L33/22

CPC classification number: H01L33/12 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/06 ,  H01L33/10 ,  H01L33/145 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/405 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

Abstract translation: 提供了使用具有图案化表面的层以改善半导体层生长的器件的方法，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。 还提供了包括这些特征中的一个或多个的装置。

公开(公告)号：US20150372193A1

公开(公告)日：2015-12-24

申请号：US13647885

申请日：2012-10-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/34 ,  H01L29/20 ,  H01L29/778 ,  H01L33/32 ,  H01L33/24

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract translation: 提供具有具有用于改善半导体层的生长的图案化表面的层的器件，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。

公开(公告)号：US20140134773A1

公开(公告)日：2014-05-15

申请号：US13647902

申请日：2012-10-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract translation: 提供了使用具有图案化表面的层以改善半导体层生长的器件的方法，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。

公开(公告)号：US10158044B2

公开(公告)日：2018-12-18

申请号：US15391922

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L31/072 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/06 ,  H01L21/02 ,  H01L29/15 ,  H01L33/02 ,  H01L33/04 ,  H01L33/20

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US10153396B2

公开(公告)日：2018-12-11

申请号：US15857853

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L27/15 ,  H01L31/0336 ,  H01L33/06 ,  H01L21/02 ,  H01L29/778 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L29/20 ,  H01L29/51 ,  H01L33/22

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20170104132A1

公开(公告)日：2017-04-13

申请号：US15391922

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L33/32 ,  H01L33/12 ,  H01L33/06 ,  H01L33/00

CPC classification number: H01L33/32 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/151 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US20170104129A1

公开(公告)日：2017-04-13

申请号：US15389479

申请日：2016-12-23

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L33/12 ,  H01L33/24 ,  H01L33/00 ,  H01L33/32 ,  H01L33/22

CPC classification number: H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/12 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09537054B2

公开(公告)日：2017-01-03

申请号：US14686845

申请日：2015-04-15

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel D. Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/06 ,  H01L33/32 ,  H01L33/00 ,  H01L21/02 ,  H01L33/20 ,  H01L33/24 ,  H01L29/15 ,  H01L29/20

CPC classification number: H01L33/12 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/155 ,  H01L29/2003 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

Abstract translation: 提供了用于制造光电子器件的异质结构。 异质结构包括诸如n型接触或包覆层的层，其包括插入其中的薄子层。 薄的子层可以遍及整个层间隔开，并由用于该层的材料制成的中间子层隔开。 薄的子层可以具有与插入的子层不同的组成，其在异质结构的生长期间改变应力存在。

公开(公告)号：US09502509B2

公开(公告)日：2016-11-22

申请号：US15083423

申请日：2016-03-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L31/00 ,  H01L29/15 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/158 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。