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11.发明授权公开(公告)号：US11444629B2
公开(公告)日：2022-09-13
申请号：US17161552
申请日：2021-01-28
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.
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12.发明授权公开(公告)号：US10452122B2
公开(公告)日：2019-10-22
申请号：US15823328
申请日：2017-11-27
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih , Yen-Hung Chen
IPC: G06F1/26 , G06F1/32 , G06F1/3234 , G06F1/3225 , G06F3/06 , G06F1/3296 , G06F13/16 , G06F13/28
Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
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公开(公告)号：US12287973B2
公开(公告)日：2025-04-29
申请号：US18225670
申请日：2023-07-24
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit. The compensation control mechanism operation logic includes a subset handle interface which generates a subset read control signal and transmits the subset read control signal to a corresponding storage circuit.
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公开(公告)号：US12249385B2
公开(公告)日：2025-03-11
申请号：US18225654
申请日：2023-07-24
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
IPC: G11C29/12
Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.
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公开(公告)号：US12235721B2
公开(公告)日：2025-02-25
申请号：US18219087
申请日：2023-07-06
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.
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Patent Agency Ranking
公开(公告)号：US12026041B2
公开(公告)日：2024-07-02
申请号：US17948254
申请日：2022-09-20
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/0751 , G06F11/0745 , H04L1/0016
Abstract: An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.
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17.发明申请公开(公告)号：US20220376694A1
公开(公告)日：2022-11-24
申请号：US17878042
申请日：2022-07-31
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.
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18.发明授权公开(公告)号：US10545694B2
公开(公告)日：2020-01-28
申请号：US15853393
申请日：2017-12-22
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih , Chia-Ching Huang
Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a thermal sensor. The thermal sensor senses ambient temperature to obtain a sensed temperature and provides the sensed temperature to the processor. When the processor determines that the sensed temperature is higher than a high-temperature threshold, the processor adjusts a data transfer speed of the predetermined interface according to a data processing speed required by subsequent data to be read from or written to the data storage device.
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公开(公告)号：US10248608B2
公开(公告)日：2019-04-02
申请号：US15837072
申请日：2017-12-11
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih , Wen-Chi Chao
Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.
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公开(公告)号：US12277288B2
公开(公告)日：2025-04-15
申请号：US18213907
申请日：2023-06-26
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results and includes a compensation control mechanism selection circuit which selects a corresponding compensation control mechanism according to the monitored results and set it as a currently-operating compensation control mechanism to control the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.
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