公开(公告)号：US20030193082A1

公开(公告)日：2003-10-16

申请号：US10175217

申请日：2002-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Po Wang ,  Chung-Chi Lin ,  Chien-Ping Huang

IPC: H01L023/495

CPC classification number: H01L24/85 ,  H01L21/565 ,  H01L23/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A chip carrier with a dam bar structure is proposed. The chip carrier is defined with at least a chip attach area and a wire bonding area surrounding the chip attach area, allowing a chip to be mounted on the chip attach area and electrically connected to the wire bonding area by bonding wires bonded to the wire bonding area. A molding gate and a dam bar are formed on the substrate outside the chip attach area and wire bonding area. An molding compound is injected through the molding gate for encapsulating the chip and bonding wires. The dam bar is provided with a first gate directed toward the molding gate, a second gate and a third gate opposed to the second gate, wherein the second and third gates are each vertically arranged with respect to the molding gate, allowing the molding compound to divert its flow direction by the dam bar.

Abstract translation: 提出了具有坝条结构的芯片载体。 芯片载体至少具有芯片附着区域和围绕芯片附着区域的引线接合区域，允许将芯片安装在芯片附着区域上，并通过接合到引线键合的引线键合电连接到引线接合区域 区。 在芯片附着区域和引线接合区域的外部的基板上形成模制门和阻挡条。 通过模制注入模塑料以封装芯片和接合线。 坝栏设置有朝向模制门的第一门，与第二门相对的第二门和第三门，其中第二和第三门相对于成型门垂直布置，允许模制化合物 通过坝条转向其流动方向。

公开(公告)号：US20030116836A1

公开(公告)日：2003-06-26

申请号：US10157069

申请日：2002-05-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L023/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract translation: 提出了具有增强的电气和热性能的BGA（球栅阵列）封装以及制造BGA封装的方法。 该BGA封装的特征在于使用功率连接散热器和接地连接散热器，其分别用于将电源焊盘和接地焊盘电连接到封装芯片，以及散发由芯片产生的热量 操作。 地面连接散热器布置成完全覆盖芯片，从而为芯片提供良好的屏蔽效果，有助于提高芯片在运行过程中的电气性能。 此外，地连接散热器部分地暴露于封装芯片的封装体的外部，由此可以实现令人满意的散热效率。

公开(公告)号：US20030096089A1

公开(公告)日：2003-05-22

申请号：US10038732

申请日：2002-01-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chien-Te Chen

IPC: B32B003/00

CPC classification number: H05K3/3442 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/24917

Abstract: A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.

Abstract translation: 提出了一种用于容纳无源部件的基板，包括由芯片附着区域限定的芯层和围绕芯片附着区域的迹线形成区域，在迹线形成区域上施加有阻焊层。 至少一对焊盘形成在迹线形成区域上，并且部分地暴露于焊料掩模层的外部。 焊盘各自形成在具有凹部的中心位置，允许芯层通过焊盘的凹部部分露出。 为了将无源部件焊接到焊盘，由于焊膏的表面张力焊接在焊盘上的焊膏形成凹陷的顶部表面，并且产生向下且会聚的拖曳力，以将无源部件适当地定位在焊盘上，而无需 产生转移或墓碑效应。

公开(公告)号：US20030057566A1

公开(公告)日：2003-03-27

申请号：US10289796

申请日：2002-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Michael Chang

IPC: H01L023/48

CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.

Abstract translation: 提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。 双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。 双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片 以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。 这种未对准的芯片布置可以帮助促进第二集成电路芯片上的焊盘的引线接合工艺。 密封剂用于封装第一集成电路芯片，第二集成电路芯片，第一组接合线，第二组接合线，第一组引线的内部和第二组的内部 的领导。 双芯片集成电路封装的特定结构不会限制两个集成电路芯片之间的相对尺寸，因此允许灵活选择两个集成电路芯片的组合。 此外，双芯片集成电路封装可以帮助节省电路板上的布局空间，并提供更多的功能和存储容量。

公开(公告)号：US20020114133A1

公开(公告)日：2002-08-22

申请号：US09774211

申请日：2001-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tzong-Da Ho ,  Chien-Ping Huang ,  Han-Ping Pu

IPC: H05K007/20

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  Y10T29/4935 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad. The proposed TBGA technology allows the resulted grounding plug to be firmly secured in position due to the filled solder being wettable to the heat sink, thereby providing a greater ball shear strength to the grounding solder ball that is subsequently bonded to the grounding plug. The finished TBGA package would be therefore assured in the reliability of its grounding structure.

Abstract translation: 提供了一种具有接地散热器的TBGA（带状球栅阵列）封装组件及其制造方法，其由带，散热器和至少一个半导体芯片构成。 所提出的TBGA技术的特征在于，通过首先在散热器中形成通孔和带中的通孔而不穿透接地焊球垫而形成接地插头，然后填充导电材料 作为焊料或银浆，从包装组件的顶部进入散热通孔，直到填充带通孔和散热通孔。 当半导体芯片安装就位时，其接地焊盘电连接到散热器，从而允许半导体芯片通过接地插头，接地焊球焊盘和连接到接地焊料的焊球进行外部接地 球垫 所提出的TBGA技术允许所得到的接地插头由于填充的焊料被润湿到散热器而牢固地固定就位，从而为接地焊球提供更大的球剪切强度，接地焊球随后与接地插头接合。 因此，完成的TBGA封装将确保其接地结构的可靠性。

公开(公告)号：US20020113308A1

公开(公告)日：2002-08-22

申请号：US09973151

申请日：2001-10-09

Applicant: Siliconware Precision Industries Co. Ltd.

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chih Chan ,  Ming-Chih Hsieh

IPC: H01L023/34

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.

Abstract translation: 提出了一种具有散热结构的半导体封装，其中散热结构精确地定位在基板上，使得多个焊球与衬底上形成的球垫自对准，并且支撑散热器 位于安装在基板上的半导体芯片的上方。 因此，在成型工序中，散热片紧密地邻接封装模具的模腔，并且防止散热片上发生树脂闪光，使得散热片的表面可以直接暴露于大气中以改善散热 效率。 此外，柔软的焊料球响应于在模制期间由封装模具产生的压力而变形。 因此，可以防止基板受到压力的损害，从而可以确保半导体封装的质量。

公开(公告)号：US20020038906A1

公开(公告)日：2002-04-04

申请号：US10001862

申请日：2001-11-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

IPC: H01L023/02

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

Abstract translation: 半导体芯片封装形成为能够通过将粘合指状物，电镀导电线和芯片载体上的迹线配置在其中，使得水分穿过并达到的路径长度来减少水分侵蚀 通过电镀导通线的接合指针显着地长于在常规芯片封装中实现的那些。

公开(公告)号：US20040058471A1

公开(公告)日：2004-03-25

申请号：US10452488

申请日：2003-05-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L021/44

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

公开(公告)号：US20040004275A1

公开(公告)日：2004-01-08

申请号：US10211422

申请日：2002-08-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Holman Chen ,  Chien-Ping Huang ,  Chin-Yuan Hong ,  Jui-Hsiang Hung ,  Chin-Teng Hsu

IPC: H01L023/495

CPC classification number: H01L21/4842 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A lead-frame-based semiconductor package and a fabrication method thereof are proposed. The semiconductor package includes: a lead frame having a plurality of first and second leads, wherein each first lead is formed with an extending portion smaller in thickness than the first lead in a manner that, an upper surface of the extending portion is flush with an upper surface of the first lead, and a lower surface of the extending portion forms a height difference with respect to a lower surface of the first lead; a chip mounted over the upper surfaces of the extending portions, and electrically connected to the leads by bonding wires; an encapsulant for encapsulating the upper surfaces of leads, upper surfaces of extending portions, chip and bonding wires; and a non-conductive material applied over the lower surfaces of extending portions, wherein the lower surfaces of leads are exposed to outside of the non-conductive material.

Abstract translation: 提出了一种引线框架半导体封装及其制造方法。 半导体封装包括：具有多个第一和第二引线的引线框架，其中每个第一引线形成有比第一引线更小的延伸部分，其延伸部分的上表面与 第一引线的上表面和延伸部的下表面相对于第一引线的下表面形成高度差; 芯片安装在延伸部分的上表面上，并通过接合线电连接到引线; 用于封装引线的上表面，延伸部分的上表面，芯片和接合线的密封剂; 以及施加在延伸部分的下表面上的非导电材料，其中引线的下表面暴露于非导电材料的外部。

公开(公告)号：US20030173680A1

公开(公告)日：2003-09-18

申请号：US10411457

申请日：2003-04-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Chin Liao ,  Han-Ping Pu ,  Chien-Ping Huang

IPC: H01L021/44

CPC classification number: H01L25/16 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.

Abstract translation: 提出了一种半导体器件及其制造方法，其中至少一个电子部件首先安装在第一基板上，然后将第一基板附接到半导体芯片或第二基板上。 此外，由于芯片沉积在第二基板上，所以在第一基板，第二基板和芯片之间建立电连接。 随后对该组合结构进行模制，球注入和分割处理，从而完成半导体器件的制造。 这样的半导体器件提供了显着的优点，包括防止线路短路的发生，不需要改变基板设计，不需要使用具有细间距的电路图案或与电子部件集成的昂贵的基板。