公开(公告)号：US20040142505A1

公开(公告)日：2004-07-22

申请号：US10420427

申请日：2003-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L021/44 ,  H01L021/48 ,  H01L023/02

CPC classification number: H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20030089983A1

公开(公告)日：2003-05-15

申请号：US10039884

申请日：2002-01-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

IPC: H01L023/48

CPC classification number: H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract translation: 提出了一种球栅阵列半导体封装，其中至少芯片安装在基板上，并且芯片上的信号焊盘通过接合线与基板上的信号指状电连接。 功率板和接地板的两端各自分别连接到芯片和基板上的预定位置，而不会妨碍接合线。 在基板上不必形成功率环或接地环，从而减少对基板的微量可路由性的限制。 此外，由于不设置电源线或接地线，因此不太可能发生接合线的短路，从而提高了生产率。 此外，功率板和接地板提供屏蔽效果，用于保护芯片免受外部电磁干扰，并且部分地与大气直接接触，以提高半导体封装的散热效率。

公开(公告)号：US20040058471A1

公开(公告)日：2004-03-25

申请号：US10452488

申请日：2003-05-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L021/44

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

公开(公告)号：US20040262033A1

公开(公告)日：2004-12-30

申请号：US10831247

申请日：2004-04-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chin-Tien Chiu ,  Chin-Huang Chang ,  Chih-Ming Huang

IPC: H05K001/03 ,  H05K003/30

CPC classification number: H05K3/305 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/0187 ,  H05K2201/09072 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.

Abstract translation: 提供一种印刷电路板及其制造方法。 制备具有芯层和其上的多对接合焊盘的衬底，其中在每对接合焊盘之间的芯层上形成有至少一个开口。 焊接掩模层覆盖芯层并填充开口，其中凹陷部分形成在焊料掩模层固化期间在开口上的焊料掩模层的位置处。 当将小的无源部件安装在印刷电路板上时，在无源部件的底部和焊料掩模层的凹部之间形成空间。 封装树脂可以流入空间，以在接合焊盘之间形成绝缘屏障，以防止接合焊盘之间的桥接和无源部件的短路。

公开(公告)号：US20040183174A1

公开(公告)日：2004-09-23

申请号：US10768307

申请日：2004-01-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L023/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract translation: 提出了具有增强的电气和热性能的BGA（球栅阵列）封装以及制造BGA封装的方法。 该BGA封装的特征在于使用功率连接散热器和接地连接散热器，其分别用于将电源焊盘和接地焊盘电连接到封装芯片，以及散发由芯片产生的热量 操作。 地面连接散热器布置成完全覆盖芯片，从而为芯片提供良好的屏蔽效果，有助于提高芯片在运行过程中的电气性能。 此外，地连接散热器部分地暴露于封装芯片的封装体的外部，由此可以实现令人满意的散热效率。

公开(公告)号：US20030116836A1

公开(公告)日：2003-06-26

申请号：US10157069

申请日：2002-05-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L023/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract translation: 提出了具有增强的电气和热性能的BGA（球栅阵列）封装以及制造BGA封装的方法。 该BGA封装的特征在于使用功率连接散热器和接地连接散热器，其分别用于将电源焊盘和接地焊盘电连接到封装芯片，以及散发由芯片产生的热量 操作。 地面连接散热器布置成完全覆盖芯片，从而为芯片提供良好的屏蔽效果，有助于提高芯片在运行过程中的电气性能。 此外，地连接散热器部分地暴露于封装芯片的封装体的外部，由此可以实现令人满意的散热效率。