公开(公告)号：US10741467B2

公开(公告)日：2020-08-11

申请号：US16593495

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/60

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

公开(公告)号：US10720403B2

公开(公告)日：2020-07-21

申请号：US16101902

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Tsai ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/78 ,  H01L23/31

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

公开(公告)号：US20200152543A1

公开(公告)日：2020-05-14

申请号：US16741243

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Shih-Yi Syu

IPC: H01L23/367 ,  H01L25/075 ,  H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

公开(公告)号：US20200006225A1

公开(公告)日：2020-01-02

申请号：US16569992

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Ju Tsou ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Pu Wang ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.

公开(公告)号：US20200006181A1

公开(公告)日：2020-01-02

申请号：US16177637

申请日：2018-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US10522439B2

公开(公告)日：2019-12-31

申请号：US15982332

申请日：2018-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Nai-Wei Liu ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/311 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor device includes a die having a pad, a passivation disposed aver the die and a portion of the pad, a polymer disposed over the passivation, a molding surrounding the die and the polymer, and an interface between the polymer and the molding. The interface and the passivation define an angle less than or greater than approximately 90°.

公开(公告)号：US10515875B2

公开(公告)日：2019-12-24

申请号：US16390138

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  Yi-Jou Lin ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Der-Chyang Yeh

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L23/538 ,  H01L23/28 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L21/768 ,  H01L21/82 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

公开(公告)号：US20190252296A1

公开(公告)日：2019-08-15

申请号：US16390138

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  Yi-Jou Lin ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Der-Chyang Yeh

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/768 ,  H01L21/82 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/28 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76843 ,  H01L21/82 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/82

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

公开(公告)号：US10366960B2

公开(公告)日：2019-07-30

申请号：US15727070

申请日：2017-10-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.

公开(公告)号：US10361161B2

公开(公告)日：2019-07-23

申请号：US15670187

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/28 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.