公开(公告)号：US20180240886A1

公开(公告)日：2018-08-23

申请号：US15437818

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L29/66045 ,  H01L23/66 ,  H01L28/40 ,  H01L29/1606 ,  H01L29/778 ,  H01L2223/6677

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

公开(公告)号：US20180151464A1

公开(公告)日：2018-05-31

申请号：US15361397

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/528 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US09882008B2

公开(公告)日：2018-01-30

申请号：US14933872

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L29/1606 ,  H01L21/02244 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786 ,  H01L51/0048 ,  H01L51/0558

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function

公开(公告)号：US20170067970A1

公开(公告)日：2017-03-09

申请号：US14936631

申请日：2015-11-09

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Archana Venugopal ,  Luigi Colombo ,  Robert R. Doering

IPC: G01R33/07 ,  H01L43/06 ,  H01L43/10 ,  H01L43/04

CPC classification number: G01R33/07 ,  G01R33/0029 ,  G01R33/0041 ,  G01R33/075 ,  G01R33/1284 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

Abstract: A Graphene Hall sensor (GHS) may be provided with a modulated gate bias signal in which the modulated gate bias signal alternates at a modulation frequency between a first voltage that produces a first conductivity state in the GHS and a second voltage that produces approximately a same second conductivity state in the GHS. A bias current may be provided through a first axis of the GHS. A resultant output voltage signal may be provided across a second axis of the Hall sensor that includes a modulated Hall voltage and an offset voltage, in which the Hall voltage is modulated at the modulation frequency. An amplitude of the Hall voltage that does not include the offset voltage may be extracted from the resultant output voltage signal.

Abstract translation: 石墨烯霍尔传感器（GHS）可以设置有调制的栅极偏置信号，其中调制的栅极偏置信号以在GHS中产生第一导电状态的第一电压和产生大致相同的第二电压之间的调制频率交替 GHS中的第二导电状态。 可以通过GHS的第一轴提供偏置电流。 可以在霍尔传感器的第二轴上提供结果输出电压信号，其包括调制霍尔电压和偏移电压，其中霍尔电压以调制频率被调制。 可以从所得到的输出电压信号中提取不包括偏移电压的霍尔电压的振幅。

公开(公告)号：US20160300775A1

公开(公告)日：2016-10-13

申请号：US15183896

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/373

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

公开(公告)号：US11984475B2

公开(公告)日：2024-05-14

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/0626 ,  H01L29/66113 ,  H01L29/861

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US20240153841A1

公开(公告)日：2024-05-09

申请号：US18544590

申请日：2023-12-19

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/373 ,  H01L21/32051 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/53209

Abstract: In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.

公开(公告)号：US11938715B2

公开(公告)日：2024-03-26

申请号：US16229668

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: B32B9/00 ,  B32B9/04 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B82Y30/00

CPC classification number: B32B9/007 ,  B32B9/041 ,  B32B9/045 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B32B2305/38 ,  B32B2457/14 ,  B82Y30/00 ,  C01P2002/20 ,  Y10T428/30

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US20230411302A1

公开(公告)日：2023-12-21

申请号：US17806954

申请日：2022-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Todd ,  Archana Venugopal

IPC: H01L23/552 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/552 ,  H01L27/0629 ,  H01L28/91

Abstract: A semiconductor device is described here. The semiconductor device includes a buried layer of a first conductivity type disposed on a semiconductor substrate. The semiconductor device includes a deep trench bypass capacitor extending into the buried layer and terminating in the buried layer. The deep trench bypass capacitor of the semiconductor device includes a first doped region, a dielectric disposed around the first doped region, and a second doped region disposed around the dielectric.

公开(公告)号：US20230170384A1

公开(公告)日：2023-06-01

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/0626 ,  H01L29/861 ,  H01L29/66113

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.