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    Digital clock-duty-cycle correction
    11.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US10033365B2

    公开(公告)日：2018-07-24

    申请号：US15598339

    申请日：2017-05-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K3/017 ,  H03K5/156 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

    Digital clock-duty-cycle correction
    12.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US09780768B2

    公开(公告)日：2017-10-03

    申请号：US14927949

    申请日：2015-10-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K5/04 ,  H03K5/156 ,  H02M3/07

    CPC classification number: H03K5/1565 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

    Charge pump
    17.
    发明授权
    Charge pump 有权

    公开(公告)号：US11411566B2

    公开(公告)日：2022-08-09

    申请号：US17397954

    申请日：2021-08-09

    Applicant: Texas Instruments Incorporated

    Inventor： Salvatore Luciano Finocchiaro ,  Tolga Dine ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

    IPC: H03L7/089 ,  H02M3/07 ,  H03L7/087

    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

    Digital clock-duty-cycle correction
    18.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US10291218B2

    公开(公告)日：2019-05-14

    申请号：US16023643

    申请日：2018-06-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K3/017 ,  H03K5/156 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

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