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公开(公告)号：US12154992B2
公开(公告)日：2024-11-26
申请号：US17402287
申请日：2021-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rahmi Hezar , Henry Litzmann Edwards , Miaad Aliroteh , Srinath Mathur Ramaswamy , Baher Haroun , Gerd Schuppener
IPC: H01L31/02 , G01S7/4861 , H01L31/107
Abstract: A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.
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公开(公告)号：US20200212899A1
公开(公告)日：2020-07-02
申请号：US16585155
申请日：2019-09-27
Applicant: Texas Instruments Incorporated
Inventor： Tolga Dinc , Salvatore Luciano Finocchiaro , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.
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3.发明授权公开(公告)号：US10483609B2
公开(公告)日：2019-11-19
申请号：US15614969
申请日：2017-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne , Gerd Schuppener , Juan Alejandro Herbsommer
Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.
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公开(公告)号：US20180309431A1
公开(公告)日：2018-10-25
申请号：US16023643
申请日：2018-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohammad Elbadry , Robert Floyd Payne , Gerd Schuppener
CPC classification number: H03K5/1565 , H02M3/07
Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.
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5.发明申请COUPLER TO LAUNCH ELECTROMAGNETIC SIGNAL FROM MICROSTRIP TO DIELECTRIC WAVEGUIDE 审中-公开从微电极到电介质波导发射电磁信号的耦合器公开(公告)号：US20160072173A1
公开(公告)日：2016-03-10
申请号：US14939128
申请日：2015-11-12
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Robert Floyd Payne , Gerd Schuppener , Baher Haroun
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
Abstract translation: 金属波导安装在多层基板上。 金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到 接触多层基板。 锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。
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Patent Agency Ranking
公开(公告)号：US20140285291A1
公开(公告)日：2014-09-25
申请号：US13854959
申请日：2013-04-02
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne , Juan Alejandro Herbsommer , Gerd Schuppener
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant.
Abstract translation: 多通道介电波导包括一组具有近似矩形的长度和截面形状的介质芯构件。芯构件具有第一介电常数值。 包层围绕该组介电芯构件并且具有低于第一介电常数的第二介电常数值。
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7.发明申请Coupler to Launch Electromagnetic Signal from Microstrip to Dielectric Waveguide 有权耦合器从微带到介质波导发射电磁信号公开(公告)号：US20140285281A1
公开(公告)日：2014-09-25
申请号：US13854947
申请日：2013-04-01
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Robert Floyd Payne , Gerd Schuppener , Baher Haroun
IPC: H01P5/107
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
Abstract translation: 金属波导安装在多层基板上。 金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到 接触多层基板。 锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。
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公开(公告)号：US11088696B2
公开(公告)日：2021-08-10
申请号：US16731739
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Salvatore Luciano Finocchiaro , Tolga Dine , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
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公开(公告)号：US20210203329A1
公开(公告)日：2021-07-01
申请号：US16731739
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Salvatore Luciano Finocchiaro , Tolga Dinc , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
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公开(公告)号：US10547297B2
公开(公告)日：2020-01-28
申请号：US16410508
申请日：2019-05-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohammad Elbadry , Robert Floyd Payne , Gerd Schuppener
Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.
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