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公开(公告)号：US11194017B2
公开(公告)日：2021-12-07
申请号：US16984262
申请日：2020-08-04
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Indu Prathapan , Karthik Ramasubramanian , Brian P. Ginsburg
Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (
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公开(公告)号：US10816655B2
公开(公告)日：2020-10-27
申请号：US15638106
申请日：2017-06-29
Applicant: Texas Instruments Incorporated
Inventor： Sachin Bharadwaj , Karthik Subburaj , Sriram Murali
IPC: G01S13/44 , G06K9/52 , G01S7/40 , G01S13/90 , G06K9/32 , G01S13/30 , G01S7/35 , G01S13/02 , G01S7/41 , G01S13/00
Abstract: A radar system is provided that includes transmission signal generation circuitry, a transmit channel coupled to the transmission generation circuitry to receive a continuous wave test signal, the transmit channel configurable to output a test signal based on the continuous wave signal in which a phase angle of the test signal is changed in discrete steps within a phase angle range, a receive channel coupled to the transmit channel via a feedback loop to receive the test signal, the receive channel including an in-phase (I) channel and a quadrature (Q) channel, a statistics collection module configured to collect energy measurements of the test signal output by the I channel and the test signal output by the Q channel at each phase angle, and a processor configured to estimate phase and gain imbalance of the I channel and the Q channel based on the collected energy measurements.
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公开(公告)号：US10782389B2
公开(公告)日：2020-09-22
申请号：US15676547
申请日：2017-08-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Ginsburg , Jawaharial Tangudu , Karthik Subburaj
IPC: G01S7/03 , G01S13/34 , G01S13/931 , H01Q1/32
Abstract: A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20170363714A1
公开(公告)日：2017-12-21
申请号：US15676547
申请日：2017-08-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Ginsburg , Jawaharial Tangudu , Karthik Subburaj
CPC classification number: G01S7/032 , G01S13/343 , G01S13/931 , H01Q1/3233
Abstract: A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20170315211A1
公开(公告)日：2017-11-02
申请号：US15642880
申请日：2017-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Brian Ginsburg , Karthik Ramasubramanian
Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.
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Patent Agency Ranking
公开(公告)号：US20170212214A1
公开(公告)日：2017-07-27
申请号：US15004443
申请日：2016-01-22
Applicant: Texas Instruments Incorporated
Inventor： Sriram Murali , Karthik Subburaj , Karthik Ramasubramanian
IPC: G01S7/35
CPC classification number: G01S7/352 , G01S7/4021 , G01S13/931 , G01S2007/358 , G01S2007/406
Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.
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公开(公告)号：US09696359B2
公开(公告)日：2017-07-04
申请号：US14588079
申请日：2014-12-31
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
CPC classification number: G01R29/26 , G01S7/03 , G01S7/4008 , G01S7/4017 , G01S13/343 , G01S13/345 , G01S13/931 , H03L7/06
Abstract: A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.
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18.发明申请公开(公告)号：US20170176574A1
公开(公告)日：2017-06-22
申请号：US14975416
申请日：2015-12-18
Applicant: Texas Instruments Incorporated
IPC: G01S7/40
Abstract: A testing device for FMCW radar includes an input for receiving a chirp signal generated by the radar. An IQ down-converter coupled to the input down-converts the chirp signal. A digitizer extracts digitized IQ signals from the down-converted chirp signal. A processor coupled to the digitizer determines at least one of frequency linearity and phase noise of the chirp signal.
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19.发明授权公开(公告)号：US12045582B2
公开(公告)日：2024-07-23
申请号：US17351699
申请日：2021-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj Gupta , Karthik Subburaj , Sujaata Ramalingam , Karthik Ramasubramanian , Indu Prathapan
CPC classification number: G06F7/49 , G06F7/501 , G06F17/142
Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.
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公开(公告)号：US12021552B2
公开(公告)日：2024-06-25
申请号：US17566047
申请日：2021-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Pranav Sinha , Mayank Kumar Singh , Rittu Sachdev , Karan Singh Bhatia , Shailesh Joshi , Indu Prathapan
CPC classification number: H04B1/0075 , H04B1/04 , H04B1/1036 , H04B1/69 , H04B2001/0408 , H04B2001/1045 , H04B2001/1063 , H04B2001/6912
Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.
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