公开(公告)号：US20240183939A1

公开(公告)日：2024-06-06

申请号：US18420133

申请日：2024-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.

公开(公告)号：US12045582B2

公开(公告)日：2024-07-23

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Subburaj ,  Sujaata Ramalingam ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US11927689B2

公开(公告)日：2024-03-12

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.