公开(公告)号：US11747397B2

公开(公告)日：2023-09-05

申请号：US17508750

申请日：2021-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318555 ,  G01R31/318572

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

公开(公告)号：US11726135B2

公开(公告)日：2023-08-15

申请号：US17858122

申请日：2022-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/26 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/2607 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318552 ,  G01R31/318594

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

公开(公告)号：US20230194604A1

公开(公告)日：2023-06-22

申请号：US18111679

申请日：2023-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/121 ,  H10K71/00 ,  G06F11/26 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318572 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/1213 ,  H10K71/00 ,  G06F11/26 ,  G01R31/31723 ,  G01R31/31727 ,  H10K59/1201

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

公开(公告)号：US20230176123A1

公开(公告)日：2023-06-08

申请号：US18102955

申请日：2023-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3183 ,  G01R31/3185 ,  G06F11/273 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318335 ,  G01R31/3172 ,  G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G06F11/2733

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer’s system. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US20230160959A1

公开(公告)日：2023-05-25

申请号：US18100178

申请日：2023-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/317 ,  G06F1/3234 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/318511 ,  G01R31/318572 ,  G01R31/318533 ,  G01R31/318575 ,  G01R31/3187 ,  G01R31/31721 ,  G01R31/318583 ,  G01R31/318555 ,  G06F1/3234 ,  G01R31/318577 ,  G01R31/318544 ,  G01R31/318563 ,  G01R31/318558 ,  G01R31/2884 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31727

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

公开(公告)号：US11644482B2

公开(公告)日：2023-05-09

申请号：US17147638

申请日：2021-01-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R1/04 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/26 ,  B05C21/00 ,  B44D3/12 ,  H05K1/11 ,  G01R1/16

CPC classification number: G01R1/0416 ,  B05C21/00 ,  B44D3/126 ,  G01R31/26 ,  G01R31/2853 ,  G01R31/2889 ,  G01R31/3177 ,  G01R31/318538 ,  H05K1/115 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

公开(公告)号：US11604222B2

公开(公告)日：2023-03-14

申请号：US17585917

申请日：2022-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G06F11/273 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/34 ,  G06F9/30

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

公开(公告)号：US20230058458A1

公开(公告)日：2023-02-23

申请号：US17982010

申请日：2022-11-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

公开(公告)号：US11549982B2

公开(公告)日：2023-01-10

申请号：US17213808

申请日：2021-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

公开(公告)号：US20220341985A1

公开(公告)日：2022-10-27

申请号：US17858122

申请日：2022-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/26 ,  G01R31/3177 ,  G01R31/3185

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.