公开(公告)号：US20230229610A1

公开(公告)日：2023-07-20

申请号：US18190242

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4027 ,  G06F2213/0038

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US11615043B2

公开(公告)日：2023-03-28

申请号：US17139970

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US20210407120A1

公开(公告)日：2021-12-30

申请号：US17474489

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T7/60 ,  G06T5/00 ,  G06T7/11 ,  G06T5/40

Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.

公开(公告)号：US20200349683A1

公开(公告)日：2020-11-05

申请号：US16930342

申请日：2020-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T5/00 ,  G06T3/00 ,  G06T5/40 ,  G06T3/40 ,  G06T7/11 ,  G06T5/20

Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.

公开(公告)号：US20190104245A1

公开(公告)日：2019-04-04

申请号：US16208313

申请日：2018-12-03

Applicant: Texas Instruments Incorporated

Inventor： Shashank Dabral ,  Rajasekhar Reddy Allu

IPC: H04N5/235 ,  H04N5/217 ,  H04N5/265 ,  H04N5/355 ,  H04N9/73

Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.

公开(公告)号：US20240427716A1

公开(公告)日：2024-12-26

申请号：US18816201

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

Abstract: Systems and methods enable data aggregation and pattern adaptation in hardware acceleration subsystems. In an example, a system, which may be a hardware thread scheduling system, includes schedulers, each associated with a pattern adapter; hardware accelerators respectively coupled to the schedulers; load store engines respectively associated with the hardware accelerators; a memory coupled to the load store engines; and a direct memory access (DMA) circuit coupled to the memory. Each pattern adapter is able to convert data from one format to another, and each load store engine is able to aggregate data elements to form larger data elements to improve overall processing efficiency.

公开(公告)号：US12143729B2

公开(公告)日：2024-11-12

申请号：US17538833

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: H04N23/84 ,  H04N9/67 ,  H04N9/68

Abstract: A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.

公开(公告)号：US20240089425A1

公开(公告)日：2024-03-14

申请号：US18510884

申请日：2023-11-16

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Brian Chae ,  Mihir Mody ,  Rajasekhar Reddy Allu

IPC: H04N17/00 ,  H04N5/14 ,  H04N7/18

CPC classification number: H04N17/004 ,  H04N5/144 ,  H04N7/183

Abstract: Devices, systems, and methods detect an image frame freeze condition. An example device includes a core logic circuit configured to generate statistics for received image data associated with an image frame, perform a census transform on pixel values of the image data to generate census transformed data, arrange the census transformed data into a binary string having a binary value, and generate transformed image data by replacing a select pixel value of the pixel values of the image data with a decimal value corresponding to the binary value; a load/store engine (LSE) coupled to the core logic circuit, the LSE configured to determine a cyclic redundancy check (CRC) value based on at least one of the image data, the transformed image data, and at least one statistic of the statistics; and an interface configured to transmit the CRC value to a host device.

公开(公告)号：US11743612B2

公开(公告)日：2023-08-29

申请号：US17555145

申请日：2021-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang Hua ,  Rajasekhar Reddy Allu ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mayank Mangla ,  Pandy Kalimuthu

IPC: H04N25/611 ,  G06T3/40 ,  G06T1/60 ,  H04N25/13

CPC classification number: H04N25/611 ,  G06T1/60 ,  G06T3/4015 ,  H04N25/13

Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules. In some embodiments, an in-pipeline CAC design is used that: is configured to perform on-the-fly CAC without any out-of-pipeline memory traffic; enables use of wide dynamic range (WDR) sensors; uses bicubic interpolation; supports vertical and horizontal chromatic aberration red/blue color channel offsets, reduces CAC line memory requirements, and supports flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

公开(公告)号：US11653105B2

公开(公告)日：2023-05-16

申请号：US17110139

申请日：2020-12-02

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Shashank Dabral ,  Mihir Narendra Mody ,  Rajasekhar Reddy Allu ,  Niraj Nandan

IPC: H04N23/88 ,  H04N23/74 ,  H04N23/71 ,  H04N9/78 ,  H04N23/76 ,  H04N23/741

CPC classification number: H04N23/88 ,  H04N9/78 ,  H04N23/71 ,  H04N23/741 ,  H04N23/76

Abstract: A method for local automatic white balance (AWB) of wide dynamic range (WDR) images is provided that includes collecting statistics for local AWB by an image signal processor (ISP) from a first WDR image generated by the ISP, receiving, by the ISP, a plurality of local gain lookup tables (LUTs), one for each color channel, wherein the plurality of local gain LUTs is generated using the statistics, and applying, by the ISP, a gain value to each pixel in a second WDR image generated by the ISP, wherein the gain value for the pixel is determined by the ISP using the local gain LUT for the color channel of the pixel.