公开(公告)号：US12242379B2

公开(公告)日：2025-03-04

申请号：US18082693

申请日：2022-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Govindarajan ,  Mohd Farooqui ,  Shailesh Ghotgalkar

IPC: G06F12/02

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

公开(公告)号：US20240411563A1

公开(公告)日：2024-12-12

申请号：US18809646

申请日：2024-08-20

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  G06F12/14 ,  G06F21/57 ,  G06F21/78 ,  H04L9/32

Abstract: An example device includes a first interface configured to couple to a first memory that is configured to store an image that includes a set of slices; a second interface configured to couple to a second memory; and a direct memory access circuit coupled to the first and second interfaces. The direct memory access circuit receives a transaction that specifies a read of a slice of the set of slices; and based on the transaction, reads the slice from the first memory; performs operations to the slice; and stores the slice in the second memory.

公开(公告)号：US12093697B2

公开(公告)日：2024-09-17

申请号：US17721534

申请日：2022-04-15

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  G06F12/14 ,  G06F21/57 ,  G06F21/78 ,  H04L9/32

CPC classification number: G06F9/4401 ,  G06F12/14 ,  G06F12/1416 ,  G06F12/1483 ,  G06F21/57 ,  H04L9/3247 ,  G06F21/78

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

公开(公告)号：US20240176488A1

公开(公告)日：2024-05-30

申请号：US18060457

申请日：2022-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Mel Alan Phipps ,  Prasad Jondhale ,  Mohd Asif Farooqui ,  Shailesh Ghotgalkar

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.