公开(公告)号：US12242377B2

公开(公告)日：2025-03-04

申请号：US18496178

申请日：2023-10-27

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Vijaya Rama Raju Kanumuri ,  Cory Dean Stewart

IPC: G06F12/00 ,  G06F9/46 ,  G06F12/02 ,  G06F12/06

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

公开(公告)号：US11947832B2

公开(公告)日：2024-04-02

申请号：US17668052

申请日：2022-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit is presented. The integrated circuit has a set of sensor input interfaces and an output interface. The integrated circuit further has a memory with a first and second memory locations. The integrated circuit further has a multi-chip hub module which has a transaction buffer with both a real-time and a non-real-time buffer. The multi-chip hub module has a context mapper, a re-formatter module and an error handling module. The context mapper is configured to map data to the first or second memory location. The multi-chip hub module is configured to process data through the modules and provide processed data to the output interface.

公开(公告)号：US11714776B2

公开(公告)日：2023-08-01

申请号：US17564975

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham Israel Vijayponraj ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

IPC: G06F13/42 ,  G06F9/4401 ,  G06F13/40 ,  G06F12/1027

CPC classification number: G06F13/4247 ,  G06F12/1027 ,  G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026 ,  G06F2213/0038

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US11704263B2

公开(公告)日：2023-07-18

申请号：US17697114

申请日：2022-03-17

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

公开(公告)号：US11693787B2

公开(公告)日：2023-07-04

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Gregory Raymond Shurtz ,  Mihir Narendra Mody ,  Charles Lance Fuoco ,  Donald E. Steiss ,  Jonathan Elliot Bergsagel ,  Jason A.T. Jones

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US11656925B2

公开(公告)日：2023-05-23

申请号：US17138036

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F9/5027 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US20220229773A1

公开(公告)日：2022-07-21

申请号：US17538662

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Vijaya Rama Raju Kanumuri ,  Cory Dean Stewart

IPC: G06F12/02 ,  G06F12/06 ,  G06F9/46

Abstract: A system is provided. In some examples, the system includes a first peripheral circuit and a memory management circuit coupled to the first peripheral circuit. The memory management circuit comprises a first table that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

公开(公告)号：US20250147672A1

公开(公告)日：2025-05-08

申请号：US18591959

申请日：2024-02-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Y.A. ,  Sriramakrishnan Govindarajan ,  Mohd Asif Farooqui ,  Shailesh Ganapat Ghotgalkar ,  Sai Karthik Rajaraman ,  Pratheesh Gangadhar TK ,  David Smith ,  Niraj Nandan

IPC: G06F3/06

Abstract: Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.

公开(公告)号：US20250036315A1

公开(公告)日：2025-01-30

申请号：US18359729

申请日：2023-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Vignesh Raghavendra ,  Mihir Mody ,  Mohammad Asif Farooqui ,  Shailesh Ghotgalkar ,  Sai Rajaraman

IPC: G06F3/06

Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. The memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. The processing circuitry executes the set of instructions.

公开(公告)号：US12050541B2

公开(公告)日：2024-07-30

申请号：US18186524

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Jason A. T. Jones

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.