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    Reconfigurable memory module and method
    11.
    发明授权
    Reconfigurable memory module and method 有权
    可重构内存模块和方法

    公开(公告)号：US07120727B2

    公开(公告)日：2006-10-10

    申请号：US10601104

    申请日：2003-06-19

    Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

    Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

    IPC: G06F12/00

    CPC classification number: G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

    Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

    Abstract translation: 计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。 存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

    Apparatus and methods for optically-coupled memory systems
    12.
    发明授权
    Apparatus and methods for optically-coupled memory systems 失效

    公开(公告)号：US06961259B2

    公开(公告)日：2005-11-01

    申请号：US10351077

    申请日：2003-01-23

    Applicant: Terry R. Lee ,  Kevin J. Ryan

    Inventor： Terry R. Lee ,  Kevin J. Ryan

    IPC: G02B6/255 ,  G11C5/06 ,  G11C7/10 ,  G11C8/02 ,  H01L29/22 ,  H01L31/109

    CPC classification number: G11C7/1054 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1081

    Abstract: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals. In another embodiment, the optical transmitter/receiver unit projects outwardly from the module substrate to provide an unobstructed path for optical signals.

    Semiconductor device with self refresh test mode
    13.
    发明授权
    Semiconductor device with self refresh test mode 失效
    具有自刷新测试模式的半导体器件

    公开(公告)号：US06856567B2

    公开(公告)日：2005-02-15

    申请号：US10408540

    申请日：2003-04-07

    Applicant: Terry R. Lee

    Inventor： Terry R. Lee

    IPC: G11C7/00 ,  G11C11/406 ,  G11C29/02 ,  G11C29/48 ,  G11C29/50 ,  G11C29/00

    CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5002

    Abstract: A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.

    Abstract translation: 半导体器件（例如DRAM）包括具有动态存储单元的存储器阵列。 在自刷新测试模式中，自刷新测试模式控制器监视和/或控制半导体器件中的各种块和内部信号。 自刷新测试模式控制器可以通过包括一个或多个DQ线和/或一个或多个地址线的各种导体与远程测试设备进行通信。

    Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
    18.
    发明授权
    Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 有权

    公开(公告)号：US06614698B2

    公开(公告)日：2003-09-02

    申请号：US09974387

    申请日：2001-10-09

    Applicant: Kevin J. Ryan ,  Terry R. Lee

    Inventor： Kevin J. Ryan ,  Terry R. Lee

    IPC: G06F1314

    CPC classification number: G06F13/161 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4093

    Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

    Simple output buffer drive strength calibration
    19.
    发明授权
    Simple output buffer drive strength calibration 失效
    简单的输出缓冲区驱动强度校准

    公开(公告)号：US06549036B1

    公开(公告)日：2003-04-15

    申请号：US09583884

    申请日：2000-05-31

    Applicant: Terry R. Lee

    Inventor： Terry R. Lee

    IPC: H03K190175

    CPC classification number: H03K19/018585

    Abstract: An output buffer driver calibration circuit and method are disclosed. Pull-up and pull-down devices of the output buffer driver circuit are simultaneously driven and the resulting output voltage is compared to a predetermined reference voltage, and a control signal is generated which is used to adjust the strength of one of the pull-up and pull-down devices so that the drive strength of the two devices approaches equality.

    Abstract translation: 公开了一种输出缓冲器驱动器校准电路和方法。 同时驱动输出缓冲器驱动电路的上拉和下拉器件，并将所得到的输出电压与预定的参考电压进行比较，并产生一个控制信号，该控制信号用于调整上拉一个的强度 和下拉装置，使得两个装置的驱动强度接近相等。

    Semiconductor device with self refresh test mode
    20.
    发明授权
    Semiconductor device with self refresh test mode 失效

    公开(公告)号：US06392948B1

    公开(公告)日：2002-05-21

    申请号：US08705149

    申请日：1996-08-29

    Applicant: Terry R. Lee

    Inventor： Terry R. Lee

    IPC: G11C700

    CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5002

    Abstract: A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen). As examples, the following signals may be analyzed and acted upon by the self refresh test mode controller, or transmitted through the self refresh test mode controller to a remote testing device: (1) internal {overscore (RAS)} signals; (2) bits from refresh counter; (3) {overscore (RAS)} chain; and (4) equilibrate signals. As examples, the following are signals that may be received or produced by the self refresh test mode controller, and then analyzed and acted upon or transmitted through the self refresh test mode controller to one or more of the various blocks of the semiconductor device: (1) a signal overriding internal {overscore (RAS)} signals generated by self refresh circuitry (including initiating a row change or the rate at which row change occurs); (2) a signal that causes control of incrementing a refresh counter; (3) signals that alter internal time or programmable delay elements.

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