公开(公告)号：US20120278524A1

公开(公告)日：2012-11-01

申请号：US13493338

申请日：2012-06-11

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G06F12/06

CPC classification number: G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract translation: 计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。 存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

公开(公告)号：US08181092B2

公开(公告)日：2012-05-15

申请号：US11639950

申请日：2006-12-15

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: H03M13/00

CPC classification number: H04B10/2504 ,  H04L1/0001 ,  H04L1/242 ,  H04L7/043

Abstract: A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract translation: 一种动态调整通信网络链路控制参数的方法和系统。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。

公开(公告)号：US20110167238A1

公开(公告)日：2011-07-07

申请号：US13047066

申请日：2011-03-14

Applicant: Joseph M. Jeddeloh ,  Terry R. Lee

Inventor： Joseph M. Jeddeloh ,  Terry R. Lee

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract translation: 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和对应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US07908452B2

公开(公告)日：2011-03-15

申请号：US12754011

申请日：2010-04-05

Applicant: Joseph M. Jeddeloh ,  Terry R. Lee

Inventor： Joseph M. Jeddeloh ,  Terry R. Lee

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract translation: 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和对应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US07716444B2

公开(公告)日：2010-05-11

申请号：US11881010

申请日：2007-07-24

Applicant: Joseph M. Jeddeloh ,  Terry R. Lee

Inventor： Joseph M. Jeddeloh ,  Terry R. Lee

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract translation: 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和相应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US20100027310A1

公开(公告)日：2010-02-04

申请号：US12577015

申请日：2009-10-09

Applicant: Terry R. Lee ,  Kevin J. Ryan

Inventor： Terry R. Lee ,  Kevin J. Ryan

IPC: G11C5/06 ,  G11C11/34 ,  G02B6/36

CPC classification number: G11C7/1054 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1081

Abstract: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals. In another embodiment, the optical transmitter/receiver unit projects outwardly from the module substrate to provide an unobstructed path for optical signals.

Abstract translation: 公开了光耦合存储器系统。 在一个实施例中，系统存储器包括载体衬底和附接到载体衬底并可操作以发射和接收光信号的控制器以及第一和第二存储器模块。 第一存储器模块的模块衬底具有形成在其中的孔，该孔可操作以为控制器和第二存储器模块的光发射器/接收器单元之间的光信号提供光路。 因此，系统存储器在紧凑的存储器模块布置中提供了“自由空间”光学连接的优点。 在替代实施例中，第一存储器模块包括在孔附近附接到模块衬底的分束器。 在另一个实施例中，第一和第二存储器模块分段在载体衬底上，以为光信号提供无阻碍的路径。 在另一个实施例中，光发射器/接收器单元从模块衬底向外突出，以提供用于光信号的无障碍路径。

公开(公告)号：US20090187714A1

公开(公告)日：2009-07-23

申请号：US12185615

申请日：2008-08-04

Applicant: Terry R. Lee ,  Joseph Jeddeloh

Inventor： Terry R. Lee ,  Joseph Jeddeloh

IPC: G06F12/02 ,  G06F15/16

CPC classification number: G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。

公开(公告)号：US07414875B2

公开(公告)日：2008-08-19

申请号：US11311948

申请日：2005-12-19

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G11C11/401

CPC classification number: G11C5/02 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09972 ,  Y02P70/611

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Abstract translation: 公开了一种用于同时可辅助存储器模块的布局。 在一个实施例中，存储器模块包括具有多个扇区的印刷电路板，每个扇区与其它扇区电隔离并且具有多层结构。 至少一个存储器装置连接到每个扇区，存储器装置被组织成多个存储器等级。 驱动器连接到印刷电路板并且可操作地耦合到存储器等级。 驱动器适于耦合到计算机系统的存储器接口。 由于扇区与相邻扇区电隔离，所以存储器排列是单独地或同时地存在的，或者由驱动器单独地并且可以同时访问，使得可以一次访问特定扇区上的一个或多个存储器件。 在替代实施例中，印刷电路板包括与其他扇区电隔离并具有多层结构的驱动器扇区，该驱动器附接到驱动器扇区。

公开(公告)号：US07376857B2

公开(公告)日：2008-05-20

申请号：US11018384

申请日：2004-12-22

Applicant: Terry R. Lee ,  Kevin J. Ryan ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Kevin J. Ryan ,  Joseph M. Jeddeloh

IPC: G06F1/12 ,  G06F5/06

CPC classification number: G01R31/31937 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814

Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Abstract translation: 提供了用于逻辑设备的定时校准的改进的技术和相关设备。 校准测试图案首先以比正常操作速度慢的数据速率传输到逻辑设备，以确保在要校准的设备上正确捕获图案。 一旦模式被正确地捕获和存储，测试模式将以正常的操作数据速率传输到逻辑设备，以执行定时校准。 改进的技术和装置允许使用任何位图案作为校准测试图案，由用户编程或使用易于互换的硬件。

公开(公告)号：US07260685B2

公开(公告)日：2007-08-21

申请号：US10601252

申请日：2003-06-20

Applicant: Terry R. Lee ,  Joseph Jeddeloh

Inventor： Terry R. Lee ,  Joseph Jeddeloh

IPC: G06F12/06

CPC classification number: G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。