公开(公告)号：US08941175B2

公开(公告)日：2015-01-27

申请号：US13918994

申请日：2013-06-17

Applicant: United Microelectronics Corp.

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC: H01L29/06 ,  H01L29/772 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract translation: 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US20210134679A1

公开(公告)日：2021-05-06

申请号：US16667921

申请日：2019-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Cheng Yang ,  Yi-Han Su ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chun-Lin Chen ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L21/8249

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

公开(公告)号：US09236471B2

公开(公告)日：2016-01-12

申请号：US14253365

申请日：2014-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US08921972B2

公开(公告)日：2014-12-30

申请号：US13896289

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L27/085 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US08890218B2

公开(公告)日：2014-11-18

申请号：US13892324

申请日：2013-05-13

Applicant: United Microelectronics Corp.

Inventor： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

公开(公告)号：US10985071B1

公开(公告)日：2021-04-20

申请号：US16667921

申请日：2019-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Cheng Yang ,  Yi-Han Su ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chun-Lin Chen ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L21/8249 ,  H01L21/8238 ,  H01L21/28

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

公开(公告)号：US10276652B1

公开(公告)日：2019-04-30

申请号：US16005652

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Ke-Feng Lin ,  Ming-Tsung Lee ,  Shih-Teng Huang ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shu-Wen Lin

IPC: H01L29/06 ,  H01L29/872

Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.

公开(公告)号：US20140339636A1

公开(公告)日：2014-11-20

申请号：US13896289

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20140225192A1

公开(公告)日：2014-08-14

申请号：US14253365

申请日：2014-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US20140131797A1

公开(公告)日：2014-05-15

申请号：US13674146

申请日：2012-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。