公开(公告)号：US20240339501A1

公开(公告)日：2024-10-10

申请号：US18143095

申请日：2023-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hsien Lin ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Chun-Chia Chen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a fin-shaped structure on the substrate, forming a gate structure on the fin-shaped structure, removing the fin-shaped structure to form a recess, forming a first epitaxial layer in the recess adjacent to the gate structure, and then forming a second epitaxial layer on the first epitaxial layer. Preferably, the semiconductor device further includes a first protrusion on one side of the first epitaxial layer and a second protrusion on another side of the first epitaxial layer.

公开(公告)号：US20240282843A1

公开(公告)日：2024-08-22

申请号：US18653933

申请日：2024-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/7834 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11742412B2

公开(公告)日：2023-08-29

申请号：US16985242

申请日：2020-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161

CPC classification number: H01L29/6656 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823821 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US10777657B2

公开(公告)日：2020-09-15

申请号：US15710820

申请日：2017-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US12009409B2

公开(公告)日：2024-06-11

申请号：US18118115

申请日：2023-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/7834 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11355619B2

公开(公告)日：2022-06-07

申请号：US16836872

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

公开(公告)号：US10651290B2

公开(公告)日：2020-05-12

申请号：US16239470

申请日：2019-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20190140077A1

公开(公告)日：2019-05-09

申请号：US16239470

申请日：2019-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3115 ,  H01L21/3105

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US10249729B1

公开(公告)日：2019-04-02

申请号：US15832696

申请日：2017-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Hsien Chen ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chih-wei Yang ,  Te-Chang Hsu

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop layer (CESL) is deposited on the composite spacer structure and the epitaxial layer. An ILD layer is deposited on the CESL. The ILD layer is polished to expose a top surface of the dummy gate. The dummy gate and a first portion of the first nitride-containing layer of the composite spacer structure are removed, thereby forming a gate trench and exposing the first gate dielectric layer. The first gate dielectric layer is removed from the gate trench, and a second portion of the first nitride-containing layer and the oxide layer are removed from the composite spacer structure, while leaving the second nitride-containing layer intact.