公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

公开(公告)号：US20160336270A1

公开(公告)日：2016-11-17

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 用于形成插头的半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成钛层以保形地覆盖凹部。 第一氮化钛层被形成为保形地覆盖钛层，由此第一氮化钛层具有第一侧壁部分。 第一氮化钛层的第一侧壁部分被拉回，从而形成第二侧壁部分。 形成第二氮化钛层以覆盖凹部。 此外，还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20140248762A1

公开(公告)日：2014-09-04

申请号：US14277812

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Nien-Ting Ho ,  Bor-Shyang Liao ,  Shu Min Huang ,  Min-Chung Cheng ,  Yu-Ru Yang

IPC: H01L21/768

CPC classification number: H01L21/76889 ,  H01L29/41791 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。 在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。 然后在去除金属层之后执行RTP。

公开(公告)号：US20240128324A1

公开(公告)日：2024-04-18

申请号：US17990763

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Chung-Yi Chiu

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1606 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/66045 ,  H01L29/78

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

公开(公告)号：US20220320420A1

公开(公告)日：2022-10-06

申请号：US17844741

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yi-Syun Chou ,  Ko-Wei Lin ,  Pei-Hsun Kao ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang ,  Chia-Chang Hsu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

公开(公告)号：US11165019B2

公开(公告)日：2021-11-02

申请号：US16576784

申请日：2019-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US10290710B2

公开(公告)日：2019-05-14

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L21/385 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US20190074357A1

公开(公告)日：2019-03-07

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/51 ,  H01L21/385 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US20170236747A1

公开(公告)日：2017-08-17

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US09679813B2

公开(公告)日：2017-06-13

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.