公开(公告)号：US10651275B2

公开(公告)日：2020-05-12

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US09859164B1

公开(公告)日：2018-01-02

申请号：US15294792

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US11791413B2

公开(公告)日：2023-10-17

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L23/10 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US20230014253A1

公开(公告)日：2023-01-19

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20190157455A1

公开(公告)日：2019-05-23

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US09722030B1

公开(公告)日：2017-08-01

申请号：US15175045

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/165 ,  H01L29/167 ,  H01L23/528 ,  H01L23/532 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20220157814A1

公开(公告)日：2022-05-19

申请号：US17131584

申请日：2020-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Ming-Shiou Hsieh ,  Zih-Hsuan Huang ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.

公开(公告)号：US10796943B2

公开(公告)日：2020-10-06

申请号：US16181354

申请日：2018-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Shi-You Liu ,  Shao-Hua Hsu

IPC: H01L21/762 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/306

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.