公开(公告)号：US20170323894A1

公开(公告)日：2017-11-09

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L29/10 ,  H01L27/088 ,  H01L27/02 ,  H01L23/532 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/0924

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

公开(公告)号：US20250142801A1

公开(公告)日：2025-05-01

申请号：US18518476

申请日：2023-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Han-Tsun Wang ,  Chang-Hung Chen

IPC: H10B10/00 ,  G11C11/412

Abstract: The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

公开(公告)号：US11489010B2

公开(公告)日：2022-11-01

申请号：US17006928

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

公开(公告)号：US20220216220A1

公开(公告)日：2022-07-07

申请号：US17163571

申请日：2021-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238

Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

公开(公告)号：US20180006038A1

公开(公告)日：2018-01-04

申请号：US15682558

申请日：2017-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Zhi-Xian Chou

IPC: H01L27/11 ,  G11C11/412 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/785

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

公开(公告)号：US09780099B1

公开(公告)日：2017-10-03

申请号：US15233961

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Zhi-Xian Chou

IPC: G11C11/04 ,  H01L27/11 ,  H01L29/78 ,  H01L27/02 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/785

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.