公开(公告)号：US12100624B2

公开(公告)日：2024-09-24

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US20240243004A1

公开(公告)日：2024-07-18

申请号：US18109225

申请日：2023-02-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Ta-Wei Chiu ,  Chia-Wen Lu ,  Wei-Lun Huang ,  Yueh-Chang Lin

IPC: H01L21/762 ,  H01L23/13

CPC classification number: H01L21/76224 ,  H01L23/13

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

公开(公告)号：US20220223720A1

公开(公告)日：2022-07-14

申请号：US17160427

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Ta-Wei Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.