公开(公告)号：US20240395883A1

公开(公告)日：2024-11-28

申请号：US18210638

申请日：2023-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Ling Wang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Yueh-Chang Lin

IPC: H01L29/423 ,  H01L21/308 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.

公开(公告)号：US20190157418A1

公开(公告)日：2019-05-23

申请号：US15846150

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/311 ,  H01L21/8234

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US12100624B2

公开(公告)日：2024-09-24

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US12046596B2

公开(公告)日：2024-07-23

申请号：US17495783

申请日：2021-10-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ping-Hung Chiang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L21/823462 ,  H01L29/0649

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

公开(公告)号：US20240243004A1

公开(公告)日：2024-07-18

申请号：US18109225

申请日：2023-02-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Ta-Wei Chiu ,  Chia-Wen Lu ,  Wei-Lun Huang ,  Yueh-Chang Lin

IPC: H01L21/762 ,  H01L23/13

CPC classification number: H01L21/76224 ,  H01L23/13

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

公开(公告)号：US20230080968A1

公开(公告)日：2023-03-16

申请号：US17495783

申请日：2021-10-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ping-Hung Chiang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

公开(公告)号：US20240355873A1

公开(公告)日：2024-10-24

申请号：US18762679

申请日：2024-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Ta-Wei Chiu

IPC: H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

公开(公告)号：US20230223306A1

公开(公告)日：2023-07-13

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US10453938B2

公开(公告)日：2019-10-22

申请号：US15846150

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US12183809B2

公开(公告)日：2024-12-31

申请号：US17673819

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.