公开(公告)号：US20180019324A1

公开(公告)日：2018-01-18

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US20170330937A1

公开(公告)日：2017-11-16

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20170294540A1

公开(公告)日：2017-10-12

申请号：US15095484

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Cheng Hu ,  Kai-Hsiang Wang ,  Tien-I Wu ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/49 ,  H01L29/161 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.

公开(公告)号：US09748386B2

公开(公告)日：2017-08-29

申请号：US14922215

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-cheng Hu ,  Tien-I Wu ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.

公开(公告)号：US09741818B2

公开(公告)日：2017-08-22

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US09214551B2

公开(公告)日：2015-12-15

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20150236158A1

公开(公告)日：2015-08-20

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US20230395719A1

公开(公告)日：2023-12-07

申请号：US18234889

申请日：2023-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L29/66553 ,  H01L21/0245 ,  H01L29/0657 ,  H01L29/6656

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US11062953B2

公开(公告)日：2021-07-13

申请号：US16676370

申请日：2019-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.