-
公开(公告)号：US10347332B2
公开(公告)日：2019-07-09
申请号：US16004705
申请日：2018-06-11
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
-
12.发明申请公开(公告)号：US20180226110A1
公开(公告)日：2018-08-09
申请号：US15868280
申请日：2018-01-11
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
CPC classification number: G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
-
公开(公告)号：US20180005694A1
公开(公告)日：2018-01-04
申请号：US15652148
申请日：2017-07-17
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
IPC: G11C13/00 , G11C8/08 , H03K3/356 , G11C8/10 , H03K19/0185
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
-
公开(公告)号：US20170025173A1
公开(公告)日：2017-01-26
申请号：US15090216
申请日：2016-04-04
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
IPC: G11C13/00 , G11C8/10 , H03K19/0185 , H03K3/356
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
Abstract translation: 系统包括交叉点存储器阵列和耦合到交叉点存储器阵列的解码器电路。 解码器电路包括具有用于产生控制信号的预解码逻辑的预解码器和产生电压信号的电平移位器电路。 解码器电路还包括耦合到预解码器的后解码器，后解码器包括耦合到第一级的第一级和第二级，控制信号以控制第一级和第二级以将电压信号通过 第一级和第二级连接到耦合到存储器阵列的多个导电阵列线的选定导电阵列线。
-
公开(公告)号：US09047928B2
公开(公告)日：2015-06-02
申请号：US14312022
申请日：2014-06-23
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.
Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。
-
Patent Agency Ranking
公开(公告)号：US20130308410A1
公开(公告)日：2013-11-21
申请号：US13693214
申请日：2012-12-04
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.
-
17.发明授权公开(公告)号：US10971227B2
公开(公告)日：2021-04-06
申请号：US16657329
申请日：2019-10-18
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Robert Norman
Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
-
18.发明申请公开(公告)号：US20200302973A1
公开(公告)日：2020-09-24
申请号：US16844487
申请日：2020-04-09
Applicant: Unity Semiconductor Corporation
Inventor： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
-
公开(公告)号：US20190392895A1
公开(公告)日：2019-12-26
申请号：US16460708
申请日：2019-07-02
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
IPC: G11C13/00 , H03K3/356 , H03K19/0185 , G11C8/10 , G11C8/08
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
-
20.发明授权公开(公告)号：US10453525B2
公开(公告)日：2019-10-22
申请号：US15823270
申请日：2017-11-27
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Robert Norman
Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
-
-
-
-
-
-
-
-
-
Search Results
55
records
(took 0.02 seconds)
