公开(公告)号：US11069386B2

公开(公告)日：2021-07-20

申请号：US16869816

申请日：2020-05-08

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  G11C7/04 ,  B82Y30/00

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US10790334B2

公开(公告)日：2020-09-29

申请号：US15633050

申请日：2017-06-26

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L45/00 ,  H01L27/24

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US10788993B2

公开(公告)日：2020-09-29

申请号：US16811401

申请日：2020-03-06

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau

IPC: G11C11/00 ,  G06F3/06 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06 ,  G11C8/08

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

公开(公告)号：US10650870B2

公开(公告)日：2020-05-12

申请号：US16276333

申请日：2019-02-14

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  G11C7/04 ,  B82Y30/00

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US20190252011A1

公开(公告)日：2019-08-15

申请号：US16276333

申请日：2019-02-14

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C8/12 ,  G11C8/10 ,  G11C13/00 ,  G11C5/02 ,  G11C11/21

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US10210917B2

公开(公告)日：2019-02-19

申请号：US15868280

申请日：2018-01-11

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  B82Y30/00 ,  G11C7/04

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US20190051701A1

公开(公告)日：2019-02-14

申请号：US16042359

申请日：2018-07-23

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20180366194A9

公开(公告)日：2018-12-20

申请号：US15868234

申请日：2018-01-11

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00 ,  G11C16/24 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20180342268A1

公开(公告)日：2018-11-29

申请号：US15984107

申请日：2018-05-18

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: G11C5/02 ,  H01L45/00 ,  G11C13/00 ,  G11C8/00 ,  H01L21/82 ,  G11C11/00 ,  H01L27/24

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

公开(公告)号：US09870809B2

公开(公告)日：2018-01-16

申请号：US15197482

申请日：2016-06-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  B82Y30/00 ,  G11C7/04

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.