公开(公告)号：US20140332252A1

公开(公告)日：2014-11-13

申请号：US13965194

申请日：2013-08-13

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/40 ,  H01L21/67265 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/67763 ,  H01L21/6779 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H05K1/11 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00

Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

Abstract translation: 载体基板包括绝缘层，导电塔和电路结构层。 每个导电塔的直径从顶表面逐渐增加到底表面，并且导电塔包括第一导电塔和围绕第一导电塔的第二导电塔。 电路结构层设置在绝缘层上，并且包括至少一个电介质层，至少两个电路层和第一导电通孔。 每个第二导电塔对应地连接到第一导电通孔中的至少两个，并且每个第一导电塔对应地连接到第一导电通孔之一。 在第一导电通孔和第一和第二导电塔之间存在界面。