公开(公告)号：US20150295090A1

公开(公告)日：2015-10-15

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

Abstract translation: 提供Fin-FET和形成Fin-FET的方法。 提供基板，然后在其上形成掩模层。 在衬底和掩模层中形成第一沟槽。 在第一沟槽中形成半导体层。 接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。 最后，在鳍结构上形成栅极层。

公开(公告)号：US20140225197A1

公开(公告)日：2014-08-14

申请号：US14261441

申请日：2014-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

Abstract translation: FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。 翅片结构设置在基板上并直接连接到基板。 此外，翅片结构包括翅片导电层和瓶颈。 绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。 门结构部分地围绕翅片结构。

公开(公告)号：US20140042640A1

公开(公告)日：2014-02-13

申请号：US14065412

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: H01L23/48

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract translation: 半导体布局图案包括设备布局图案，具有第一尺寸的多个矩形第一虚设图案，具有变化的第二尺寸的多个矩形第二虚设图案以及比第二虚设图形小的多个第一通孔虚设图案， 在第二虚拟图案内的空间范围内。