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    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME
    4.
    发明申请
    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
    FINFET晶体管结构及其制造方法

    公开(公告)号：US20140252482A1

    公开(公告)日：2014-09-11

    申请号：US14288369

    申请日：2014-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

    IPC: H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

    Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。

    DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS
    5.
    发明申请
    DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS 有权
    DUMMY PATTERNS和生成DUMMY PATTERNS的方法

    公开(公告)号：US20140042636A1

    公开(公告)日：2014-02-13

    申请号：US14064219

    申请日：2013-10-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

    IPC: H01L23/48

    CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

    Abstract translation: 一种用于产生虚拟图案的方法包括提供具有第一密度的布局图案的布局区域，在布局图案中插入具有与第一密度对应的第二密度的多个第一伪图案，将布局区域分成多个子图 具有第三密度的区域，根据第二密度和第三密度之间的差来调整第一伪图案的尺寸，并将布局图案和第一伪图案输出到光掩模上。

    Metal-gate CMOS device and fabrication method thereof
    6.
    发明授权
    Metal-gate CMOS device and fabrication method thereof 有权
    金属栅CMOS器件及其制造方法

    公开(公告)号：US08592271B2

    公开(公告)日：2013-11-26

    申请号：US13895376

    申请日：2013-05-16

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

    IPC: H01L21/8238 ,  H01L21/70

    CPC classification number: H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

    Abstract translation: 一种制造金属栅CMOS器件的方法。 提供其上具有第一区域和第二区域的基板。 第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。 第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。 第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。 然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。 第一区域用密封层掩蔽。 此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。

    METAL-GATE CMOS DEVICE AND FABRICATION METHOD THEREOF
    10.
    发明申请
    METAL-GATE CMOS DEVICE AND FABRICATION METHOD THEREOF 有权
    金属门CMOS器件及其制造方法

    公开(公告)号：US20130252387A1

    公开(公告)日：2013-09-26

    申请号：US13895376

    申请日：2013-05-16

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

    IPC: H01L21/8234

    CPC classification number: H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

    Abstract translation: 一种制造金属栅CMOS器件的方法。 提供其上具有第一区域和第二区域的基板。 第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。 第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。 第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。 然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。 第一区域用密封层掩蔽。 此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。

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