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公开(公告)号:US20160218105A1
公开(公告)日:2016-07-28
申请号:US14634903
申请日:2015-03-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Ming Lee
IPC: H01L27/092 , H01L29/06 , H01L29/165 , H01L21/3105 , H01L21/324 , H01L21/02 , H01L29/66 , H01L21/311
CPC classification number: H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/7856 , H01L2029/7858
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, wherein the fin-shaped structure comprises a top portion and a bottom portion; removing part of the bottom portion of the fin-shaped structure; forming an epitaxial layer on the substrate to surround the bottom portion of the fin-shaped structure; transforming the bottom portion of the fin-shaped structure into the epitaxial layer; and removing part of the epitaxial layer.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供其上具有至少一个鳍状结构的基底,其中所述鳍状结构包括顶部和底部; 去除所述鳍状结构的底部的一部分; 在所述基板上形成外延层以包围所述鳍状结构的底部; 将鳍状结构的底部转变成外延层; 并去除外延层的一部分。
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12.
公开(公告)号:US12100756B2
公开(公告)日:2024-09-24
申请号:US17528159
申请日:2021-11-16
Applicant: United Microelectronics Corp.
Inventor: Hao-Ming Lee , Ta Kang Lo , Tsai-Fu Chen , Shou-Wei Hsieh
IPC: H01L29/778 , H01L29/06 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7786 , H01L29/0607 , H01L29/2003 , H01L29/401 , H01L29/41775 , H01L29/42316 , H01L29/66462 , H01L29/7783 , H01L2924/13064
Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.
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公开(公告)号:US10068963B2
公开(公告)日:2018-09-04
申请号:US14936370
申请日:2015-11-09
Applicant: United Microelectronics Corp.
Inventor: Huai-Tzu Chiang , Sheng-Hao Lin , Hao-Ming Lee , Yu-Ru Yang , Shih-Hsien Huang , Chien-Hung Chen , Chun-Yuan Wu , Cheng-Tzung Tsai
IPC: H01L29/78 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/10 , H01L29/66 , H01L21/225 , H01L21/768
Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
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公开(公告)号:US09954082B1
公开(公告)日:2018-04-24
申请号:US15598260
申请日:2017-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Ming Lee , Sheng-Hao Lin , Tzyy-Ming Cheng
IPC: H01L21/00 , H01L27/00 , H01L29/00 , H01L29/66 , H01L27/11568 , H01L27/11521 , H01L29/51 , H01L21/027
CPC classification number: H01L29/66795 , H01L21/28282 , H01L27/1157 , H01L29/517 , H01L29/66545 , H01L29/66833 , H01L29/792
Abstract: A method of fabricating an embedded nonvolatile memory device is disclosed. A semiconductor substrate having thereon a fin body protruding from an isolation layer is provided. A charge storage layer crossing the fin body is formed. An inter-layer dielectric layer is deposited on the semiconductor substrate. The inter-layer dielectric layer is polished to expose a top surface of the charge storage layer. The charge storage layer is then recess etched and cut into separate charge storage structures. A high-k dielectric layer is formed on the charge storage structures. A word line is formed on the high-k dielectric layer.
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公开(公告)号:US09871102B2
公开(公告)日:2018-01-16
申请号:US14684443
申请日:2015-04-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsin-Yu Chen , Huai-Tzu Chiang , Sheng-Hao Lin , Hao-Ming Lee
IPC: H01L29/66 , H01L29/06 , H01L29/78 , H01L29/786 , H01L29/423 , H01L21/02 , H01L29/10
CPC classification number: H01L29/0673 , H01L21/02532 , H01L21/02667 , H01L21/3247 , H01L29/0649 , H01L29/1083 , H01L29/42392 , H01L29/66742 , H01L29/7848 , H01L29/786
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.
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公开(公告)号:US09698218B2
公开(公告)日:2017-07-04
申请号:US15221617
申请日:2016-07-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsin-Yu Chen , Sheng-Hao Lin , Huai-Tzu Chiang , Hao-Ming Lee
IPC: H01L29/06 , H01L21/02 , B82Y30/00 , B82Y40/00 , H01L21/324 , H01L21/306 , H01L29/10
CPC classification number: H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02164 , H01L21/0217 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L21/02664 , H01L21/30604 , H01L21/3247 , H01L29/0669 , H01L29/1033 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.
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公开(公告)号:US20170062430A1
公开(公告)日:2017-03-02
申请号:US15350113
申请日:2016-11-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Ming Lee
IPC: H01L27/092 , H01L29/06 , H01L21/762 , H01L21/8238 , H01L21/3105 , H01L21/02 , H01L21/324 , H01L29/165 , H01L29/66 , H01L21/311
CPC classification number: H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/7856 , H01L2029/7858
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least one fin-shaped structure thereon, wherein the fin-shaped structure comprises a top portion and a bottom portion; removing part of the bottom portion of the fin-shaped structure; forming an epitaxial layer on the substrate to surround the bottom portion of the fin-shaped structure; transforming the bottom portion of the fin-shaped structure into the epitaxial layer; and removing part of the epitaxial layer.
Abstract translation: 一种用于制造半导体器件的方法包括以下步骤:提供其上具有至少一个鳍状结构的衬底,其中所述鳍状结构包括顶部和底部; 去除所述鳍状结构的底部的一部分; 在所述基板上形成外延层以包围所述鳍状结构的底部; 将鳍状结构的底部转变成外延层; 并去除外延层的一部分。
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公开(公告)号:US20160268375A1
公开(公告)日:2016-09-15
申请号:US14684443
申请日:2015-04-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsin-Yu Chen , Huai-Tzu Chiang , Sheng-Hao Lin , Hao-Ming Lee
IPC: H01L29/06 , H01L29/786 , H01L29/10 , H01L29/423 , H01L21/311 , H01L21/02 , H01L29/78 , H01L29/66
CPC classification number: H01L29/0673 , H01L21/02532 , H01L21/02667 , H01L21/3247 , H01L29/0649 , H01L29/1083 , H01L29/42392 , H01L29/66742 , H01L29/7848 , H01L29/786
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.
Abstract translation: 半导体器件及其形成方法,该半导体器件包括单晶衬底,源/漏结构和纳米线结构。 源极/漏极结构设置在衬底上并与衬底接触。 纳米线结构连接到源极/漏极结构。
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公开(公告)号:US20180323256A1
公开(公告)日:2018-11-08
申请号:US16040319
申请日:2018-07-19
Applicant: United Microelectronics Corp.
Inventor: Huai-Tzu Chiang , Sheng-Hao Lin , Hao-Ming Lee , Yu-Ru Yang , Shih-Hsien Huang , Chien-Hung Chen , Chun-Yuan Wu , Cheng-Tzung Tsai
IPC: H01L29/06 , H01L29/10 , H01L21/768 , H01L29/66 , H01L29/78 , H01L21/225
CPC classification number: H01L29/0615 , H01L21/2253 , H01L21/76802 , H01L21/76871 , H01L29/1033 , H01L29/1054 , H01L29/66795 , H01L29/785
Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
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公开(公告)号:US20180053826A1
公开(公告)日:2018-02-22
申请号:US15797011
申请日:2017-10-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chien-Hung Chen , Shih-Hsien Huang , Yu-Ru Yang , Huai-Tzu Chiang , Hao-Ming Lee , Sheng-Hao Lin , Cheng-Tzung Tsai , Chun-Yuan Wu
IPC: H01L29/165 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/3065 , H01L29/06 , H01L21/02 , H01L21/306
CPC classification number: H01L29/165 , H01L21/02532 , H01L21/02609 , H01L21/30604 , H01L21/3065 , H01L29/0657 , H01L29/1054 , H01L29/66795 , H01L29/785
Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.
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