公开(公告)号：US07211200B2

公开(公告)日：2007-05-01

申请号：US10369273

申请日：2003-02-18

Applicant: Gary Chen ,  Li Li ,  Yongjun Jeff Hu

Inventor： Gary Chen ,  Li Li ,  Yongjun Jeff Hu

IPC: C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  H01L21/302

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32134

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract translation: 金属氮化物和金属氮氧化合物通常在金属硅化物上形成。 这些挤压可能导致短路并降低加工产量。 本发明公开了一种选择性地去除这种挤出物的方法。 在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。 在另一个实施方案中，湿蚀刻包括调节蚀刻的pH以选择性地相对于字线中的其它物质去除某些挤出物的碱。 因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

公开(公告)号：US07090815B2

公开(公告)日：2006-08-15

申请号：US11100573

申请日：2005-04-07

Applicant: Yongjun Jeff Hu ,  Er-Xuan Ping

Inventor： Yongjun Jeff Hu ,  Er-Xuan Ping

IPC: C01B33/12 ,  C01B33/00 ,  H01L27/14

CPC classification number: B01J37/0244 ,  B01J21/08 ,  B01J23/40 ,  B01J23/74 ,  B01J27/24 ,  B01J37/0238

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

公开(公告)号：US06849544B2

公开(公告)日：2005-02-01

申请号：US10454218

申请日：2003-06-04

Applicant: Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

Inventor： Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

IPC: H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L21/44

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/32105

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract translation: 用于半导体器件的导电结构包括多层结构。 第一层包括含硅的材料，例如多晶硅和锗锗。 在第一层上形成阻挡层，阻挡层包括金属硅化物或金属硅化物氮化物。 在阻挡层上形成顶部导电层。 顶部导电层可以包括金属或金属硅化物。 可以进行选择性氧化以减少包含多层结构的结构中所选材料的氧化量，例如多层导电结构。 选择性氧化在单晶片快速热处理系统中进行，其中使用包括氢的所选择的环境来确保所选择的材料如钨或金属氮化物的低氧化。

公开(公告)号：US06831343B2

公开(公告)日：2004-12-14

申请号：US10659728

申请日：2003-09-10

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L3100

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

公开(公告)号：US06717351B2

公开(公告)日：2004-04-06

申请号：US09779508

申请日：2001-02-09

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01J162

CPC classification number: H01J9/025 ,  H01J2201/30407

Abstract: An emission site for a large area passive matrix cold cathode field emission display having an emission tip with a sharp profile is disclosed. A metallic film formed of iridium silicide (IrSi) is used to coat the tip. By using IrSi the tips of the emission sites can be formed at low temperatures. In addition, IrSi is a fine grain material that maintains a sharp profile and can be formed in a layer as thin as 100 A°.

Abstract translation: 公开了具有具有尖锐轮廓的发射尖端的大面积无源矩阵冷阴极场发射显示器的发射场所。 使用由铱硅化物（IrSi）形成的金属膜来涂覆尖端。 通过使用IrSi，可以在低温下形成发射部位的尖端。 此外，IrSi是细晶粒材料，其保持锋利的轮廓，并且可以形成为薄至100A°的层。

公开(公告)号：US06688584B2

公开(公告)日：2004-02-10

申请号：US09858617

申请日：2001-05-16

Applicant: Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

Inventor： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC: H01L2940

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

公开(公告)号：US06509239B1

公开(公告)日：2003-01-21

申请号：US09429236

申请日：1999-10-28

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC: H01L21336

CPC classification number: H01L29/41783 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L29/41775 ,  H01L29/7834

Abstract: In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on substantially amorphous material, and forming elevated source/drains on the doped source/drain regions. In but another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material. Capacitor forming methods are also disclosed.

Abstract translation: 在本发明的一个方面，沉积多晶硅的方法包括在化学气相沉积反应器内提供衬底，衬底具有暴露的基本上结晶的区域和暴露的基本无定形区域。 包含硅的气体前体在有效基本上选择性地在结晶区域而非非晶区域上沉积多晶硅的条件下被供给到化学气相沉积反应器。 在另一方面，在衬底上制造场效应晶体管的方法包括形成栅极介电层和半导体材料上的栅极。 掺杂的源极/漏极区域在靠近栅极的半导体材料内形成。 基本上非晶绝缘材料形成在栅极上方和侧向靠近栅极。 衬底设置在化学气相沉积反应器内。 包含硅的气体前体在有效地基本上选择性地在源极/漏极区域上沉积多晶硅而不是基本上无定形材料的条件下被馈送到化学气相沉积反应器，并且在掺杂源极/漏极区上形成升高的源极/漏极。 在另一方面，公开了一种形成与基板的接触的方法。 接触开口在最终包括向外暴露的基本上结晶的表面的节点位置上通过非晶绝缘材料蚀刻。 在化学气相沉积反应器内，在有效地基本上选择性地将多晶硅沉积在外露的晶体结点位置表面而不是在绝缘材料上的条件下提供包含硅的气态前体。 还公开了电容器形成方法。

公开(公告)号：US06328620B1

公开(公告)日：2001-12-11

申请号：US09205197

申请日：1998-12-04

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01J904

CPC classification number: H01J9/025 ,  H01J2201/30407

Abstract: An emission site for a large area passive matrix cold cathode field emission display having an emission tip with a sharp profile is disclosed. A metallic film formed of iridium silicide (IrSi) is used to coat the tip. By using IrSi the tips of the emission sites can be formed at low temperatures. In addition, IrSi is a fine grain material that maintains a sharp profile and can be formed in a layer as thin as 100 Å.

公开(公告)号：US6147405A

公开(公告)日：2000-11-14

申请号：US26104

申请日：1998-02-19

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L23/485 ,  H01L23/58 ,  B32B15/04

CPC classification number: H01L23/485 ,  H01L2924/0002

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiN.sub.x), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x

公开(公告)号：US6074960A

公开(公告)日：2000-06-13

申请号：US914935

申请日：1997-08-20

Applicant: Whonchee Lee ,  Yongjun Jeff Hu

Inventor： Whonchee Lee ,  Yongjun Jeff Hu

IPC: C23F1/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H.sub.2 SO.sub.4, H.sub.3 PO.sub.4, HNO.sub.3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide. An etching composition including a mineral acid and a peroxide, preferably, HCl and hydrogen peroxide, is also described. The etching methods and compositions may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.