公开(公告)号：US20110099806A1

公开(公告)日：2011-05-05

申请号：US12929090

申请日：2010-12-30

Applicant: Tetsuya Koyama ,  Tsuyoshi Kobayashi ,  Hiroyuki Kato ,  Yoshihiro Machida

Inventor： Tetsuya Koyama ,  Tsuyoshi Kobayashi ,  Hiroyuki Kato ,  Yoshihiro Machida

IPC: H05K3/36

CPC classification number: H05K3/4614 ,  H05K3/462 ,  H05K3/4647 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1327 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.

公开(公告)号：US07923367B2

公开(公告)日：2011-04-12

申请号：US11907889

申请日：2007-10-18

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L21/4763

CPC classification number: H05K1/186 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/4602 ,  H05K2201/09845 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first opening, a supporting layer which is formed on the other surface of the core material layer and which supports the electronic component, a plurality of connection conductor sections which are provided around the first opening and within the second opening on the one surface of the core material layer, bonding wires for electrically connecting the electronic component to the connection conductor sections, and a sealing resin filled into the first and second openings in order to seal the electronic component and the bonding wires.

Abstract translation: 安装有电子部件的多层布线基板包括电子部件，具有容纳电子部件的第一开口的芯材层，形成在芯材层的一个面上的树脂层，其具有大于 所述第一开口，形成在所述芯材料层的另一个表面上并且支撑所述电子部件的支撑层，多个连接导体部，所述多个连接导体部设置在所述第一开口的周围，并且位于所述第一开口的一个表面上 芯材料层，用于将电子部件电连接到连接导体部分的接合线以及填充到第一和第二开口中的密封树脂，以密封电子部件和接合线。

公开(公告)号：US07786580B2

公开(公告)日：2010-08-31

申请号：US11870743

申请日：2007-10-11

Applicant: Yoshihiro Machida ,  Takaharu Yamano

Inventor： Yoshihiro Machida ,  Takaharu Yamano

IPC: H01L21/60

CPC classification number: H01L23/3114 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014

Abstract: A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

Abstract translation: 半导体芯片的特征在于包括其上形成有电极焊盘的半导体芯片的结构，形成在各个电极焊盘上的凸起，并且具有突出部分，形成在半导体芯片上的绝缘层和要连接的导电图案 到凸块，其中突出部分的末端插入到导电图案中，并且插入的末端被平坦化。

公开(公告)号：US07772109B2

公开(公告)日：2010-08-10

申请号：US11724265

申请日：2007-03-15

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L21/4763

CPC classification number: H05K3/4614 ,  H05K1/0393 ,  H05K3/0052 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4635 ,  H05K2201/0195 ,  H05K2201/055 ,  H05K2201/09536 ,  H05K2203/061

Abstract: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.

Abstract translation: 在基板101的两个表面101A，101B上同时形成第一多层布线结构体16和第二多层布线结构体56，然后将对应于第三区域C1的结构体120的部分折叠成与 第二结构体22与第二结构体62和第一多层布线结构体16电连接到第二多层布线结构体56。

公开(公告)号：US07772091B2

公开(公告)日：2010-08-10

申请号：US12212169

申请日：2008-09-17

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L21/304

CPC classification number: H01L23/544 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: Alignment patterns are formed in scribe regions of a semiconductor substrate, and through grooves for exposing the scribe regions are disposed in an insulating layer formed on the semiconductor substrate. Formation positions of wiring patterns are aligned based on the alignment patterns, and a metal layer is patterned and the wiring patterns are formed.

Abstract translation: 在半导体衬底的划线区域中形成对准图案，并且通过用于暴露刻划区域的沟槽设置在形成在半导体衬底上的绝缘层中。 基于对准图案对配线图案的形成位置进行图案化，形成配线图案。

公开(公告)号：US20090309231A1

公开(公告)日：2009-12-17

申请号：US12485601

申请日：2009-06-16

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes: a first insulating layer having an opening therethrough; a first wiring pattern disposed on the first insulating layer; an external connection terminal provided on a portion of the first wiring pattern exposed from the opening; a second insulating layer which covers the first wiring pattern and having via holes therethrough; a second wiring pattern disposed within the second insulating layer and electrically connected to the first wiring pattern via a conductive material filled in at least one of the via holes; a semiconductor element having an electrode thereon and mounted on the second insulating layer to be electrically connected to the first wiring pattern through the electrode disposed in at least one of the via holes; an underfill resin filled between the semiconductor element and the second insulating layer; and a sealing resin portion which seals the semiconductor element.

Abstract translation: 半导体器件包括：具有穿过其中的开口的第一绝缘层; 布置在所述第一绝缘层上的第一布线图案; 设置在从所述开口露出的所述第一布线图案的一部分上的外部连接端子; 第二绝缘层，其覆盖所述第一布线图案并且具有穿过其的通孔; 第二布线图案，设置在所述第二绝缘层内并且经由填充在至少一个所述通孔中的导电材料电连接到所述第一布线图案; 半导体元件，其上具有电极，并且安装在第二绝缘层上，以通过布置在至少一个通孔中的电极电连接到第一布线图案; 填充在所述半导体元件和所述第二绝缘层之间的底部填充树脂; 以及密封半导体元件的密封树脂部分。

公开(公告)号：US20090127665A1

公开(公告)日：2009-05-21

申请号：US12273901

申请日：2008-11-19

Applicant: Takaharu Yamano ,  Yoshihiro Machida

Inventor： Takaharu Yamano ,  Yoshihiro Machida

IPC: H01L21/304 ,  H01L23/58

CPC classification number: H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/10 ,  H01L2224/02333 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.

Abstract translation: 一种制造半导体器件的方法，具有制备具有多个半导体芯片形成区域的半导体衬底和布置在多个半导体芯片形成区域之间并包括衬底切割位置的划线区域的准备步骤，半导体芯片形成步骤 在所述多个半导体芯片形成区域上形成具有电极焊盘的半导体芯片，在所述半导体芯片上形成第一绝缘层和所述半导体基板的划线区域的第一绝缘层形成步骤，形成第二绝缘层形成工序， 除了与基板切断位置对应的区域之外的第一绝缘层上的绝缘层，以及在基板切断位置切断半导体基板的切断工序。

公开(公告)号：US07521283B2

公开(公告)日：2009-04-21

申请号：US11257717

申请日：2005-10-25

Applicant: Yoshihiro Machida ,  Takaharu Yamano

Inventor： Yoshihiro Machida ,  Takaharu Yamano

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A manufacturing method of a chip integrated substrate is disclosed. The manufacturing method includes a first step that forms a wiring structure to be connected to a semiconductor chip on a first core substrate; a second step that disposes the semiconductor chip on a second core substrate; and a third step that bonds the first core substrate on which the wiring structure is formed to the second core substrate on which the semiconductor chip is disposed. In addition, the manufacturing method includes a step that removes the first core substrate after the third step and a step that removes the second core substrate after the third step.

Abstract translation: 公开了一种芯片集成基板的制造方法。 该制造方法包括：形成与第一芯基板上的半导体芯片连接的布线结构的第一工序; 将所述半导体芯片配置在第二芯基板上的第二工序; 以及将其上形成有布线结构的第一芯基板结合到其上设置有半导体芯片的第二芯基板的第三步骤。 此外，该制造方法包括在第三步骤之后去除第一芯基板的步骤和在第三步骤之后去除第二芯基板的步骤。

公开(公告)号：US20070047920A1

公开(公告)日：2007-03-01

申请号：US11508209

申请日：2006-08-23

Applicant: Yoshihiro Machida ,  Nobuhiro Tsutsumi ,  Kouji Kamogawa

Inventor： Yoshihiro Machida ,  Nobuhiro Tsutsumi ,  Kouji Kamogawa

IPC: H04N7/26

CPC classification number: H04N21/4312 ,  G06F3/0481 ,  G06F3/04847 ,  G06F3/04886 ,  G06F2203/04803 ,  G11B19/025 ,  G11B27/3027 ,  G11B27/34 ,  G11B27/36 ,  H04N21/4122 ,  H04N21/4263 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/44222 ,  H04N21/466 ,  H04N21/47217

Abstract: A digital content reproducing apparatus is provided with a plurality of user operation interfaces, e.g., a linear content operation panel and an interactive content operation panel, a data monitor unit monitors information on digital contents, and upon occurrence of a change, the plurality of user operation panels are automatically and exclusively displayed in an operation panel display area. Accordingly, only usable operation keys can be displayed, user operation learning time can be shortened, since the panel rendering area is made small, a mouse motion distance can be shortened, and easy to use can be improved. Further, since the panel rendering area is made small, the image display area can be made relatively large.

Abstract translation: 数字内容再现装置具有多个用户操作界面，例如线性内容操作面板和交互式内容操作面板，数据监视单元监视关于数字内容的信息，并且在发生改变时，多个用户 操作面板将自动并专门显示在操作面板显示区域中。 因此，只要能够显示可使用的操作键，就可以缩短用户操作学习时间，因为面板渲染区域变小，可以缩短鼠标移动距离，并且可以提高易用性。 此外，由于面板渲染区域变小，可以使图像显示区域相对较大。

公开(公告)号：US20050286873A1

公开(公告)日：2005-12-29

申请号：US11165214

申请日：2005-06-24

Applicant: Kouji Kamogawa ,  Masayuki Inoue ,  Yoko Morimoto ,  Hiroshi Sasamoto ,  Yoshihiro Machida

Inventor： Kouji Kamogawa ,  Masayuki Inoue ,  Yoko Morimoto ,  Hiroshi Sasamoto ,  Yoshihiro Machida

IPC: G11B20/10 ,  H04N5/76 ,  H04N5/92 ,  H04N19/00 ,  H04N19/115 ,  H04N19/136 ,  H04N19/157 ,  H04N19/70 ,  H04N7/26

CPC classification number: G11B20/10 ,  H04N19/115

Abstract: A video and audio recorder and a method of operating the same. The recorder includes a TV signal receiving unit, a video/audio compression recording control unit for compressing the video and audio signals and outputting a compressed video/audio multiplex data at the time of recording a program, an accumulation recording unit for recording the compressed video/audio multiplex data in a recording medium, and a recording control unit for controlling the video/audio compression recording control unit thereby to control the program recording operation. The recording control unit, based on the program information of the program to be recorded, controls the program recording operation by setting proportion information between the video recording bit rate and the audio recording bit rate in the compression process of the video and audio signals in the video/audio compression recording control unit.

Abstract translation: 视频和录音机及其操作方法。 记录器包括电视信号接收单元，视频/音频压缩记录控制单元，用于在录制节目时压缩视频和音频信号并输出​​压缩的视频/音频多路复用数据，用于记录压缩视频的累积记录单元 /音频复用数据，以及记录控制单元，用于控制视频/音频压缩记录控制单元从而控制节目记录操作。 记录控制单元基于要记录的节目的节目信息，通过在视频和音频信号的压缩处理中在视频记录比特率和音频记录比特率之间设置比例信息来控制节目记录操作 视频/音频压缩记录控制单元。