公开(公告)号：US07393774B2

公开(公告)日：2008-07-01

申请号：US11459645

申请日：2006-07-25

Applicant: Ming-Yen Chiu

Inventor： Ming-Yen Chiu

IPC: H01L21/4763

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/538 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/007 ,  H05K3/06 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2924/00

Abstract: A method of fabricating microconnectors. A wafer is provided, and a dielectric layer is formed on a first surface of the wafer. The dielectric layer is bonded to a support wafer, and a thinning process is performed. A second surface of the wafer is then bonded to the support wafer, and a conductive wiring pattern is formed on the dielectric layer. An insulating layer is formed on the dielectric layer and the conductive wiring pattern. A portion of the insulating layer is removed to expose the conductive wiring pattern, and a portion of the dielectric layer and the wafer is removed to divide the wafer into a plurality of microconnectors.

Abstract translation: 一种制造微型连接器的方法。 提供晶片，并且在晶片的第一表面上形成电介质层。 将电介质层接合到支撑晶片上，进行变薄处理。 然后将晶片的第二表面接合到支撑晶片，并且在电介质层上形成导电布线图案。 在电介质层和导电布线图案上形成绝缘层。 绝缘层的一部分被去除以暴露导电布线图案，并且去除介电层和晶片的一部分以将晶片分成多个微型连接器。

公开(公告)号：US07987588B2

公开(公告)日：2011-08-02

申请号：US12273550

申请日：2008-11-19

Applicant: Kuan-Jui Huang ,  Chang-Ping Wang ,  Hsiu-Ming Li ,  Shih-Min Huang ,  Hui-Chen Kuo ,  Chia-Chun Chen

Inventor： Kuan-Jui Huang ,  Chang-Ping Wang ,  Hsiu-Ming Li ,  Shih-Min Huang ,  Hui-Chen Kuo ,  Chia-Chun Chen

IPC: H05K3/02

CPC classification number: H01L25/0657 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L2224/14 ,  H01L2224/16237 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/49109 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract translation: 本发明公开了一种用于连接多个芯片的插入器。 插入器包括连接基板和设置在连接基板中的至少通孔。 连接基板具有第一表面和第二表面。 通孔作为连接器，并且电连接到第一表面和第二表面。 第一表面和第二表面分别电连接至至少第一芯片和第二芯片。 此外，第一芯片和第二芯片通过通孔电连接。

公开(公告)号：US07741772B2

公开(公告)日：2010-06-22

申请号：US11736595

申请日：2007-04-18

Applicant: Hung-Yi Lin ,  Hong-Da Chang

Inventor： Hung-Yi Lin ,  Hong-Da Chang

IPC: H01J1/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L33/50 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A white light emitting diode package structure having a silicon substrate is disclosed. The white light emitting diode package structure comprises a silicon substrate having a plurality of cup-structures thereon, one of a plurality of blue light emitting diodes is respectively disposed in each cup-structure, and a phosphor structure covering the silicon substrate and the cup-structures. The blue light emitting diodes have various wavelengths and the phosphor structure has a plurality of kinds of phosphor powders and a sealing material. Each kind of phosphor powder is able to convert blue light within a certain wavelength into yellow light.

Abstract translation: 公开了一种具有硅衬底的白色发光二极管封装结构。 白色发光二极管封装结构包括其上具有多个杯结构的硅衬底，在每个杯结构中分别设置多个蓝色发光二极管中的一个，并且覆盖硅衬底和杯状结构的荧光体结构， 结构。 蓝色发光二极管具有各种波长，并且荧光体结构具有多种荧光体粉末和密封材料。 各种荧光粉能够将一定波长内的蓝光转换为黄光。

公开(公告)号：US07622334B2

公开(公告)日：2009-11-24

申请号：US12100392

申请日：2008-04-09

Applicant: Chun-Wei Tsai ,  Shih-Feng Shao

Inventor： Chun-Wei Tsai ,  Shih-Feng Shao

IPC: H01L21/44

CPC classification number: B81C1/00873 ,  B81C2203/0118 ,  H01L23/10 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cutting method for wafer-level packaging capable of protecting the contact pad, in which several cavities and precutting lines are formed at the front surface of a cap wafer, and the depth of each precutting line is lesser than the thickness of the cap wafer, followed by the bonding of the cap wafer to the device wafer, which has several devices and several bonding pads disposed on the surface of the device wafer, followed by performing a wafer dicing process, along the precutting lines cutting through the cap wafer, and after removing a portion of the cap wafer that is not bonded to the device wafer, for exposing the bonding pads at the surface of the device wafer, and finally performing a dicing process for forming many packaged dies.

Abstract translation: 一种用于晶片级封装的切割方法，其能够保护接触焊盘，其中在盖晶片的前表面处形成有多个空腔和预切割线，并且每个预切割线的深度小于盖晶片的厚度， 接着将盖晶片与装置晶片的接合，该器件晶片具有设置在器件晶片表面上的若干器件和多个焊盘，随后沿切割穿过盖晶片的预切割线进行晶片切割处理，之后 去除未结合到器件晶片的盖晶片的一部分，用于暴露器件晶片表面处的接合焊盘，并且最后进行用于形成许多封装管芯的切割工艺。

公开(公告)号：US07598125B2

公开(公告)日：2009-10-06

申请号：US11426573

申请日：2006-06-26

Applicant: Shih-Feng Shao ,  Ming-Yen Chiu

Inventor： Shih-Feng Shao ,  Ming-Yen Chiu

IPC: H01L21/00

CPC classification number: H01L23/04 ,  B81B7/0041 ,  B81B2201/047 ,  H01L21/4817 ,  H01L2924/0002 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract translation: 通过未被图案化光致抗蚀剂覆盖的区域蚀刻具有空腔的盖片晶片，以形成多个开口。 盖晶片在具有空腔的表面处结合到透明晶片，并且围绕空腔分段以形成多个帽结构。 盖结构被密封到器件晶片，以在位于器件晶片上的器件和焊盘上形成密封窗。

公开(公告)号：US07582511B2

公开(公告)日：2009-09-01

申请号：US11434734

申请日：2006-05-17

Applicant: Chen Hsiung Yang

Inventor： Chen Hsiung Yang

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/5227 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.

Abstract translation: 本发明提供一种晶片级芯片级封装结构，其包括管芯，至少一个无源部件，组合层，隔离层，至少一个连接线，内部焊盘和钝化层。 模具包括浅连接焊盘，内部焊盘和电气部件。 被动部件形成在模具的一侧。 组合层增加了被动部件和模具之间的结合力。 模具另一侧的部分表面与隔离层重叠。 隔离层和内部焊盘的部分表面与连接线重叠以电连接到内部焊盘，并且钝化层用于保护管芯。

公开(公告)号：US07528000B2

公开(公告)日：2009-05-05

申请号：US11735501

申请日：2007-04-16

Applicant: Chun-Wei Tsai

Inventor： Chun-Wei Tsai

IPC: H01L21/00

CPC classification number: H01L31/18 ,  H01L31/0203

Abstract: A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of the plate corresponding to the through holes is not in contact with the glass wafer. A voltage source is provided, and two electrodes thereof respectively have electrical connections to the wafer and the plate. The wafer and the glass wafer are bonded to each other by the anodic bonding method so that a plurality of optical device caps are formed.

Abstract translation: 提供具有多个通孔的晶片，并且玻璃晶片设置在晶片上。 具有多个凹腔的板设置在玻璃晶片上，其中与晶片的通孔相对应的凹腔使得对应于通孔的板的一部分不与玻璃晶片接触。 提供电压源，其两个电极分别具有与晶片和板的电连接。 晶片和玻璃晶片通过阳极接合方法彼此接合，从而形成多个光学器件盖。

公开(公告)号：US07514287B2

公开(公告)日：2009-04-07

申请号：US11308303

申请日：2006-03-15

Applicant: Ter-Chang Huang ,  Hung-Yi Lin ,  Wen-Syang Hsu

Inventor： Ter-Chang Huang ,  Hung-Yi Lin ,  Wen-Syang Hsu

IPC: H01L21/00

CPC classification number: B81C1/00587 ,  B81C2201/0133

Abstract: A method for reducing dimension of an MEMS device. A single crystalline substrate having a diaphragm is provided. A first-step anisotropic dry etching process is performed to form an opening corresponding to the diaphragm in the back surface, the anisotropic dry etching stopping on a specific lattice plane extending from the edge of the diaphragm. A second-step anisotropic wet etching process is performed to etch the single crystalline substrate along the specific lattice plane until the diaphragm is exposed to form a cavity having a diamond-like shape.

Abstract translation: 一种减小MEMS器件尺寸的方法。 提供具有隔膜的单晶衬底。 执行第一步各向异性干法蚀刻工艺以形成与背面中的隔膜对应的开口，各向异性干蚀刻停止在从隔膜的边缘延伸的特定晶格面上。 执行第二步各向异性湿蚀刻工艺以沿着特定的晶格平面蚀刻单晶衬底，直到膜片暴露以形成具有菱形形状的空腔。

公开(公告)号：US07510892B2

公开(公告)日：2009-03-31

申请号：US11737133

申请日：2007-04-18

Applicant: Hung-Yi Lin ,  Hong-Da Chang

Inventor： Hung-Yi Lin ,  Hong-Da Chang

IPC: H01L21/00

CPC classification number: H01L33/486 ,  H01L33/60 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure.

Abstract translation: 发光二极管结构具有硅衬底，导电层和发光二极管。 硅衬底的顶表面具有杯结构像抛物面，并且杯结构的底部具有贯穿硅衬底的多个通孔。 导电层填充通孔并从通孔突出。 发光二极管设置在从通孔突出的导电层的顶部，并且位于杯结构的焦点处。

公开(公告)号：US07361284B2

公开(公告)日：2008-04-22

申请号：US11426013

申请日：2006-06-23

Applicant: Chih-Hsien Chen

Inventor： Chih-Hsien Chen

IPC: H01B13/00

CPC classification number: H01L23/10 ,  B81C1/00333 ,  B81C2203/0127 ,  H01L23/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to the cavities is removed so that the remaining cap wafer forms a plurality of support blocks. A device wafer is provided, and the support blocks are bonded to the device wafer so that the support blocks and the transparent wafer hermitically seal the devices disposed in the device wafer.

Abstract translation: 晶圆级封装的方法。 将具有空穴的盖片结合到支撑晶片上，并且盖晶片的一部分被蚀刻通过。 盖晶片从支撑晶片释放并结合到透明晶片，并且去除与空腔相对应的盖晶片的一部分，使得剩余的盖晶片形成多个支撑块。 提供了器件晶片，并且支撑块被结合到器件晶片，使得支撑块和透明晶片密封地密封设置在器件晶片中的器件。