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公开(公告)号：US12024422B2
公开(公告)日：2024-07-02
申请号：US17161367
申请日：2021-01-28
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Enri Duqi , Lorenzo Baldo , Domenico Giusti
CPC classification number: B81C1/00238 , B81B7/0051 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2203/0118 , B81B2203/0127 , B81B2203/0315 , B81B2207/012 , B81B2207/07 , B81C2201/0133 , B81C2203/032 , B81C2203/035 , B81C2203/0792
Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.
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2.发明授权公开(公告)号：US11952268B2
公开(公告)日：2024-04-09
申请号：US17304094
申请日：2021-06-14
Inventor： Chantal Arena , Nupur Bhargava , Alec Fischer
CPC classification number: B81C1/00476 , B81B3/0072 , B81B2203/0118 , B81C2201/0109 , B81C2201/0132 , B81C2201/0133 , B81C2201/0177
Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.
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公开(公告)号：US11946822B2
公开(公告)日：2024-04-02
申请号：US17290140
申请日：2019-10-16
Applicant: Sciosense B.V.
Inventor： Alessandro Faes , Jörg Siegert , Willem Frederik Adrianus Besling , Remco Henricus Wilhelmus Pijnenburg
CPC classification number: G01L9/0073 , B81B3/0021 , B81C1/00595 , G01L9/0042 , B81B2201/0264 , B81B2203/0127 , B81B2207/015 , B81C2201/0109 , B81C2201/0133 , B81C2201/014
Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.
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公开(公告)号：US11939216B2
公开(公告)日：2024-03-26
申请号：US17188082
申请日：2021-03-01
Applicant: Infineon Technologies AG
Inventor： Andre Brockmeier , Stephan Helbig , Adolf Koller
CPC classification number: B81C1/00904 , B81C1/00888 , G02B26/0833 , G02B26/105 , B81B2201/042 , B81C2201/0132 , B81C2201/0133 , B81C2201/0143
Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.
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公开(公告)号：US20230399754A1
公开(公告)日：2023-12-14
申请号：US18207569
申请日：2023-06-08
Applicant: ENTEGRIS, INC.
Inventor： Daniela White , Michael L. White , YoungMin Kim , Akshay Rajopadhye , Atanu K. Das
CPC classification number: C23G1/18 , B81C1/00857 , B81C2201/0142 , B81C2201/0133
Abstract: The present disclosure relates to removal compositions for at least partially removing post-chemical mechanical polishing (post-CMP) residues from the surface of a microelectronic device. The removal compositions comprise an aqueous base composition and various molybdenum etching inhibitors that reduce the amount of molybdenum removed from the surface of the microelectronic device compared to the aqueous base composition.
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Patent Agency Ranking
公开(公告)号：US11787688B2
公开(公告)日：2023-10-17
申请号：US17099442
申请日：2020-11-16
Applicant: KNOWLES ELECTRONICS, LLC
Inventor： Sung Bok Lee , Vahid Naderyan , Bing Yu , Michael Kuntzman , Yunfei Ma , Michael Pedersen
CPC classification number: B81C1/00158 , B81B3/0021 , G01L9/0042 , H04R31/003 , B81B2201/0257 , B81B2201/0264 , B81B2203/0127 , B81C2201/0132 , B81C2201/0133
Abstract: A method of forming an acoustic transducer comprises providing a substrate and depositing a first structural layer on the substrate. The first structural layer is selectively etched to form at least one of an enclosed trench or an enclosed pillar thereon. A second structural layer is deposited on the first structural layer and includes a depression or a bump corresponding to the enclosed trench or pillar, respectively. At least the second structural layer is heated to a temperature above a glass transition temperature of the second structural layer causing the second structural layer to reflow. A diaphragm layer is deposited on the second structural layer such that the diaphragm layer includes at least one of a downward facing corrugation corresponding to the depression or an upward facing corrugation corresponding to the bump. The diaphragm layer is released, thereby forming a diaphragm suspended over the substrate.
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公开(公告)号：US11731125B2
公开(公告)日：2023-08-22
申请号：US16639867
申请日：2019-01-03
Inventor： Yue Geng , Yuelei Xiao , Hui Liao , Peizhi Cai , Jian Li , Shenkang Wu
CPC classification number: B01L3/502707 , B81C1/00071 , B01L2200/12 , B01L2300/12 , B01L2400/086 , B81C2201/0133
Abstract: A patterning method of a film is disclosed. The method including: providing a film including a first surface; forming n etching barrier layers on the first surface of the film, and n is an integer larger than or equal to 2; and performing n etching processes on the film to form a recessed structure on the first surface using the n etching barrier layers as masks, the recessed structure includes n bottom surfaces respectively having different depths. Two adjacent etching processes of the n etching processes include a previous etching process and a subsequent etching process, and after the previous etching process is completed, a part of the n etching barrier layers is removed to form a mask for the subsequent etching process; a material of the part of the n etching barrier layers which is removed is different from a material of the mask of the subsequent etching process.
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8.发明申请公开(公告)号：US20180170748A1
公开(公告)日：2018-06-21
申请号：US15899785
申请日：2018-02-20
Applicant: Globalfoundries Singapore Pte. Ltd.
Inventor： Siddharth Chakravarty , Rakesh Kumar , Pradeep Yelehanka
CPC classification number: B81C1/00293 , B81B7/0074 , B81B2203/0315 , B81C2201/0105 , B81C2201/0132 , B81C2201/0133 , B81C2203/0136
Abstract: Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes providing a substrate terminating at an uppermost surface and forming a sacrificial structure over the uppermost substrate of the substrate. The method includes forming a device structure overlying a lower portion of the sacrificial structure, overlying the uppermost surface of the substrate, and underlying an upper portion of the sacrificial structure. The method also includes depositing a permeable layer over the sacrificial structure, the device structure and the substrate. Further, the method includes etching the sacrificial structure through the permeable layer to form the cavity, wherein the cavity has an outer surface completely bounded by the substrate, the device structure, and the permeable layer.
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9.发明申请公开(公告)号：US20180148325A1
公开(公告)日：2018-05-31
申请号：US15591652
申请日：2017-05-10
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Enri Duqi , Lorenzo Baldo , Domenico Giusti
CPC classification number: B81C1/00238 , B81B7/0051 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2203/0118 , B81B2203/0127 , B81B2203/0315 , B81B2207/012 , B81B2207/07 , B81C2201/0133 , B81C2203/032 , B81C2203/035 , B81C2203/0792
Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.
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公开(公告)号：US09919916B2
公开(公告)日：2018-03-20
申请号：US15031957
申请日：2014-10-15
Applicant: Semitechnologies Limited
CPC classification number: B81C1/00111 , A61M37/0015 , A61M2037/003 , A61M2037/0053 , B81B2201/055 , B81C2201/0132 , B81C2201/0133 , B81C2201/0159 , B81C2201/0176 , B81C2201/0181 , C23C16/402
Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
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