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公开(公告)号:US07262078B2
公开(公告)日:2007-08-28
申请号:US10906972
申请日:2005-03-15
Applicant: Wei-Shun Lai , Shu-Hua Hu , Kuan-Jui Huang , Chin-Chang Pan , Yuan-Chin Hsu
Inventor: Wei-Shun Lai , Shu-Hua Hu , Kuan-Jui Huang , Chin-Chang Pan , Yuan-Chin Hsu
IPC: H01L21/44
CPC classification number: B81C1/00365 , B81C2201/0132 , B81C2201/018 , H01L23/3192 , H01L24/11 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/1147 , H01L2224/13006 , H01L2224/13099 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00014 , H01L2224/05552 , H01L2924/013
Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.
Abstract translation: 提供基板。 衬底包括设置在衬底中的多个器件,设置在衬底的表面上并电连接到器件的多个接触焊盘以及位于衬底表面上的表面电介质层。 此后,进行至少包括等离子体蚀刻工艺的表面处理工艺。 随后,至少进行等离子体增强化学气相沉积(PECVD)工艺以在表面电介质层上形成电介质层。 以高频/低频交替方式执行PECVD处理。 接着,形成电介质层上的掩模图案,进行各向异性蚀刻处理,以形成对应于电介质层中的接触焊盘的多个开口。 这些开口暴露接触垫,并且每个开口具有向外倾斜的侧壁。
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公开(公告)号:US20060109534A1
公开(公告)日:2006-05-25
申请号:US11264361
申请日:2005-11-01
Applicant: Thomas Grebinski
Inventor: Thomas Grebinski
IPC: G02B5/32
CPC classification number: B81C1/00682 , B81B2201/042 , B81B2203/0109 , B81C2201/0104 , B81C2201/018 , G02B26/0833 , G02B26/0841
Abstract: The present invention relates to producing ultra flat micro surfaces suitable, for instance, for micro-mirrors. In particular, it relates to low pressure chemical mechanical planarization (CMP) of a partially cured sacrificial layer.
Abstract translation: 本发明涉及生产适合于例如微镜的超平面微表面。 特别地,其涉及部分固化的牺牲层的低压化学机械平面化(CMP)。
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公开(公告)号:US20020132101A1
公开(公告)日:2002-09-19
申请号:US10104749
申请日:2002-03-22
Applicant: The Penn State Research Foundation
Inventor: Stephen J. Fonash , Alikaan Kalkan , Sanghoon Bae
IPC: B32B003/26
CPC classification number: B81C1/0038 , B81C1/00047 , B81C2201/0115 , B81C2201/0139 , B81C2201/018 , C23C16/24 , C23C16/511 , G01N21/17 , G01N27/121 , G01N27/44717 , G01N30/6095 , H01J49/0418 , Y10T428/24174 , Y10T428/249953
Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250 null C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.
Abstract translation: 公开了一种新颖的多孔膜,其包括在连续空隙中的硅柱网络,其可以在低温下(即小于约250℃)下使用高密度等离子体沉积来制造。该硅膜是二维纳米尺寸阵列 的棒状柱。 这种空隙柱形态可以用沉积条件控制,并且孔隙率可以变化高达90%。 在所采用的等离子体方法中同时使用低温沉积和蚀刻允许在同时获得柱状结构,连续空隙和多晶柱组成的独特机会。 可以使用这种多孔连续膜通过将该膜等离子体沉积在玻璃,金属箔,绝缘体或塑料基底上来制造独特的器件。
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