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    Simulating access lines
    12.
    发明授权
    Simulating access lines 有权

    公开(公告)号：US09704541B2

    公开(公告)日：2017-07-11

    申请号：US15179338

    申请日：2016-06-10

    Applicant: Micron Technology, Inc.

    Inventor： Jeremiah J. Willcock

    IPC: G11C7/08 ,  G11C7/06 ,  G11C5/06 ,  G11C11/4096 ,  G11C7/10 ,  G11C19/00

    CPC classification number: G11C7/065 ,  G11C5/066 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1036 ,  G11C7/1063 ,  G11C7/1069 ,  G11C11/4096 ,  G11C19/00

    Abstract: Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.

    Semiconductor apparatus and operating method thereof
    15.
    发明授权
    Semiconductor apparatus and operating method thereof 有权
    半导体装置及其操作方法

    公开(公告)号：US09576620B2

    公开(公告)日：2017-02-21

    申请号：US14636814

    申请日：2015-03-03

    Applicant: SK hynix Inc.

    Inventor： Ho Sung Cho

    IPC: G11C19/00 ,  G11C7/10 ,  G06F9/30 ,  G11C16/32 ,  H03M9/00 ,  G11C29/12 ,  G11C16/10

    CPC classification number: G11C7/1036 ,  G06F9/30105 ,  G06F9/30134 ,  G11C16/10 ,  G11C16/32 ,  G11C29/1201 ,  H03M9/00

    Abstract: A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data.

    Abstract translation: 一种半导体装置，包括寄存器输入选择块，被配置为串行地接收输入数据并且并行地输出输入数据作为第一和第二数据组，或者接收寄存器选择输出信号，并且将寄存器选择输出信号作为第一和第二数据集输出， 响应于移位控制信号和捕获控制信号; 第一数据寄存器，被配置为接收和存储第一数据组，并将存储的数据作为第一寄存器输出信号输出; 第二数据寄存器，被配置为接收和存储第一和第二数据组并输出存储的数据作为第二寄存器输出信号; 寄存器输出选择块，被配置为输出第一和第二寄存器输出信号中的一个作为寄存器选择输出信号; 以及数据输出选择块，被配置为串行地输出第一和第二数据集之一作为输出数据。

    TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS
    16.
    发明申请
    TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS 审中-公开
    双引脚串行总线通信接口和过程

    公开(公告)号：US20170011783A1

    公开(公告)日：2017-01-12

    申请号：US15270673

    申请日：2016-09-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G11C7/10 ,  G06F13/42

    CPC classification number: G11C7/1036 ,  G01R31/318572 ,  G06F3/0601 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4291 ,  G11C7/1066 ,  H04L29/08549

    Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

    Abstract translation: 双引脚通信接口总线和控制电路与集成电路中的电路板，集成电路或嵌入式核心一起使用。 一个引脚将数据双向传输，并将地址和指令信息从控制器传送到所选端口。 另一个引脚将时钟信号从控制器传送到所需电路或电路中或其上的目标端口或端口。 总线可用于串行访问电路，其中IC上的引脚或芯上的端子的可用性最小。 总线用于通信，例如与IC或核心设计的功能操作有关的串行通信，或与IC或核心设计的测试，仿真，调试和/或跟踪操作相关的串行通信。

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    17.
    发明申请
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开

    公开(公告)号：US20160358636A1

    公开(公告)日：2016-12-08

    申请号：US15238186

    申请日：2016-08-16

    Applicant: lntel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G11C7/10

    CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    LOOP STRUCTURE FOR OPERATIONS IN MEMORY
    18.
    发明申请
    LOOP STRUCTURE FOR OPERATIONS IN MEMORY 有权
    内存中操作的环路结构

    公开(公告)号：US20160225422A1

    公开(公告)日：2016-08-04

    申请号：US15013269

    申请日：2016-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari ,  Kyle Wheeler

    IPC: G11C8/04 ,  G11C7/00

    CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/12 ,  G11C8/04 ,  G11C11/4091 ,  G11C11/4094

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

    Abstract translation: 本公开的示例提供了与在存储器中执行的操作执行循环结构相关的装置和方法。 示例性装置还可以包括控制器，其被配置为使得感测电路经由环路结构遍历多个第一元件和多个第二元件，以使用多个第一元件和多个第二元件执行操作，其中a 与循环结构相关联的条件语句用于确定存储为迭代器掩码的多个比特中的至少一个是否具有特定的比特值。 示例性装置还可以包括可控制的感测电路，以在循环结构的每次迭代时使用迭代器掩码执行移位操作，并且在循环结构的每次迭代时使用迭代器掩码执行AND运算。

    Remote memory ring buffers in a cluster of data processing nodes
    20.
    发明授权
    Remote memory ring buffers in a cluster of data processing nodes 有权
    数据处理节点集群中的远程内存环缓冲区

    公开(公告)号：US09304896B2

    公开(公告)日：2016-04-05

    申请号：US13959428

    申请日：2013-08-05

    Applicant: III Holdings 2, LLC

    Inventor： Prashant R. Chandra ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Niall Joseph Dalton

    IPC: G06F12/00 ,  G06F15/173 ,  G06F12/02

    CPC classification number: G06F12/00 ,  G06F9/54 ,  G06F12/0223 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/17375 ,  G11C7/1036 ,  G11C7/1072 ,  G11C21/00 ,  Y02D10/14

    Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.

    Abstract translation: 数据处理节点具有节点间消息传递模块，其包括多个寄存器组，每组寄存器定义GET / PUT上下文的实例和多个数据处理核心，每个数据处理核心耦合到节点间消息传递模块。 每个数据处理核心包括映射功能，用于将多个用户级过程中的每一个映射到寄存器组中的不同的一个，从而映射到相应的GET / PUT上下文实例。 将每个用户级进程映射到不同的一组寄存器使得特定的一个用户级进程能够利用其相应的GET / PUT上下文实例来执行GET / PUT动作到不同的环形缓冲区 数据处理节点通过结构耦合到数据处理节点，而不涉及任何一个数据处理核心的操作系统。

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