公开(公告)号：US20140008768A1

公开(公告)日：2014-01-09

申请号：US14005975

申请日：2012-04-03

Applicant: Michito Sato

Inventor： Michito Sato

IPC: H01L29/34 ,  H01L21/02

CPC classification number: H01L29/34 ,  H01L21/0201 ,  H01L21/02024

Abstract: A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.

Abstract translation: 在抛光时在外周形成有凹陷的半导体晶片，其中半导体晶片在厚度方向上的位移在半导体晶片的中心和外周起始位置之间为100nm以下，中心 半导体晶片的外周凹陷量为100nm以下，外周凹陷开始位置远离半导体晶片的外周部朝向中心或20mm，或者 更远离半导体晶片的外周端朝向中心，外周部​​是ESFQR的测量对象。

公开(公告)号：US20130285264A1

公开(公告)日：2013-10-31

申请号：US13539243

申请日：2012-06-29

Applicant: I-Hsiung HUANG ,  Heng-Hsin LIU ,  Heng-Jen LEE ,  Chin-Hsiang LIN

Inventor： I-Hsiung HUANG ,  Heng-Hsin LIU ,  Heng-Jen LEE ,  Chin-Hsiang LIN

IPC: H01L23/544 ,  H01L21/02

CPC classification number: H01L21/0201 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

Abstract translation: 晶片组件包括处理晶片和载体晶片。 集成电路形成在处理晶片上。 载体晶片结合到工艺晶片。 载体晶片具有至少一个对准标记。

公开(公告)号：US20130269368A1

公开(公告)日：2013-10-17

申请号：US13912907

申请日：2013-06-07

Applicant: Lam Research Corporation

Inventor： Keith William GAFF ,  Keith Comendant ,  Anthony Ricci

IPC: F25B21/04 ,  H01L35/34 ,  H01L21/02

CPC classification number: F25B21/04 ,  H01L21/0201 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H01L35/34 ,  Y10T29/49083 ,  Y10T29/49165

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract translation: 在半导体等离子体处理装置中用于衬底支撑组件的热板包括以可伸缩复用布局布置的多个可独立控制的平面热区，以及用于独立地控制和供电平面加热器区的电子装置。 每个平面热区使用至少一个珀耳帖装置作为热电元件。 其中结合有热敏板的基板支撑组件具有静电夹持电极层和温度控制的基板。 用于制造热板的方法包括将具有平面热区域，正，负和公共线路和通孔的陶瓷或聚合物片材结合在一起。

公开(公告)号：US20130244405A1

公开(公告)日：2013-09-19

申请号：US13747046

申请日：2013-01-22

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Masanori Terahara ,  Hikaru Kokura ,  Akihiro Hasegawa ,  Atsuo Fushida ,  Fumihiko Akaboshi

IPC: H01L21/02

CPC classification number: H01L21/0201 ,  H01J37/321 ,  H01L21/32137 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6831

Abstract: A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.

Abstract translation: 制造本文公开的半导体器件的方法包括：将衬底安装在放置在室内的静电吸盘上，所述静电吸盘具有第一温度，并且所述衬底预先保持在具有低于第一温度的第二温度的气氛中; 通过向静电卡盘施加电压将基板固定到静电卡盘上; 在安装基板之后，将静电卡盘加热至高于第一温度和第二温度的第三温度; 并在加热之后处理基板。

公开(公告)号：US20130152852A1

公开(公告)日：2013-06-20

申请号：US13706966

申请日：2012-12-06

Applicant: Crystal IS, Inc.

Inventor： Robert T. Bondokov ,  Kenneth E. Morgan ,  Glen A. Slack ,  Leo Schowalter

IPC: C30B25/02 ,  B28D5/00

CPC classification number: C30B33/02 ,  B28D5/00 ,  C23C16/34 ,  C30B23/00 ,  C30B23/02 ,  C30B25/02 ,  C30B25/08 ,  C30B25/10 ,  C30B25/18 ,  C30B29/403 ,  H01L21/0201 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/30625 ,  Y10T428/21

Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm−2 and an inclusion density below 104 cm−3 and/or a MV density below 104 cm−3.

Abstract translation: 降低AlN中的微孔（MV）密度改善了与晶体生长期间的开裂有关的许多问题，抛光期间的蚀刻坑产生，AlN晶片中的光学透明度的降低以及可能的AlN的外延生长期间的生长凹坑形成和/ 或AlGaN。 这有助于实际的晶体生产策略和形成具有低缺陷密度（例如，位错密度低于104cm -2）和包含密度低于104cm -3和/或低于104cm -3的MV密度的大体积AlN晶体 。

公开(公告)号：US20090309191A1

公开(公告)日：2009-12-17

申请号：US12137328

申请日：2008-06-11

Applicant: Horst Theuss

Inventor： Horst Theuss

IPC: H01L21/268 ,  H01L29/04 ,  H01L21/67

CPC classification number: H01L21/268 ,  H01L21/0201 ,  H01L21/78

Abstract: A semiconductor device includes a wafer having a first surface opposite a second surface, and at least one laser irradiated region between the first and second surfaces. The laser irradiated region includes a laser-induced stress that is configured to minimize curvature of at least one of the first and second surfaces.

Abstract translation: 半导体器件包括具有与第二表面相对的第一表面的晶片和在第一和第二表面之间的至少一个激光照射区域。 激光照射区域包括被配置为最小化第一表面和第二表面中的至少一个的曲率的激光诱发应力。

公开(公告)号：US11761118B2

公开(公告)日：2023-09-19

申请号：US17619516

申请日：2020-06-30

Applicant: SHIN-ETSU HANDOTAI CO., LTD.

Inventor： Weifeng Qu ,  Shizuo Igawa ,  Ken Sunakawa

IPC: B32B9/00 ,  C30B31/02 ,  C30B29/06 ,  C30B33/02 ,  H01L21/02

CPC classification number: C30B31/02 ,  C30B29/06 ,  C30B33/02 ,  H01L21/0201

Abstract: A method for manufacturing a carbon-doped silicon single crystal wafer, including steps of: preparing a silicon single crystal wafer not doped with carbon; performing a first RTA treatment on the silicon single crystal wafer in an atmosphere containing compound gas; performing a second RTA treatment at a higher temperature than the first RTA treatment; cooling the silicon single crystal wafer after the second RTA treatment; and performing a third RTA treatment. The crystal wafer is modified to a carbon-doped silicon single crystal wafer, sequentially from a surface thereof: a 3C-SiC single crystal layer; a carbon precipitation layer; a diffusion layer of interstitial carbon and silicon; and a diffusion layer of vacancy and carbon. A carbon-doped silicon single crystal wafer having a surface layer with high carbon concentration and uniform carbon concentration distribution to enable wafer strength enhancement; and a method for manufacturing the carbon-doped silicon single crystal wafer.

公开(公告)号：US20180331252A1

公开(公告)日：2018-11-15

申请号：US15363050

申请日：2016-11-29

Applicant: PALO ALTO RESEARCH CENTER INCORPORATED

Inventor： MAX BATRES ,  ZHIHONG YANG ,  THOMAS WUNDERER

IPC: H01L33/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/306 ,  H01L29/20 ,  H01L29/32 ,  H01L33/32 ,  H01L33/02 ,  H01S5/323 ,  H01S5/183

CPC classification number: H01L33/0079 ,  H01L21/0201 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02634 ,  H01L21/30625 ,  H01L21/7806 ,  H01L29/2003 ,  H01L29/32 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/32 ,  H01S5/183 ,  H01S5/32308 ,  H01S2304/04

Abstract: A method of thinning a bulk aluminum nitride substrate includes providing a bulk aluminum nitride (AlN) substrate with at least one epitaxially grown group-III-nitride layer on a first side of the substrate, applying a slurry having a high pH to a second side of the substrate opposite the first side, chemical mechanically polishing the second side of the substrate using the slurry to remove at least a portion of the substrate, resulting in a thinned layer with a thickness less than 50 microns, and bonding the epitaxial layer to a non-native substrate. A device has at least one active zone in a layer of epitaxial Group-III-nitride material, the epitaxial Group-III-nitride layer having a defect density of less than or equal to 108/cm2.

公开(公告)号：US09945048B2

公开(公告)日：2018-04-17

申请号：US13525041

申请日：2012-06-15

Applicant: Sen-Hong Syue ,  Pu-Fang Chen ,  Shiang-Bau Wang

Inventor： Sen-Hong Syue ,  Pu-Fang Chen ,  Shiang-Bau Wang

IPC: C30B15/04 ,  H01L21/02 ,  C30B15/20 ,  C30B31/02 ,  C30B31/04 ,  H01L21/311 ,  C30B15/22 ,  H01L29/36 ,  H01L21/762 ,  C30B31/16 ,  H01L21/3105 ,  C30B29/06 ,  H01L21/322 ,  C30B15/00 ,  C30B33/00 ,  H01L29/78

CPC classification number: C30B15/04 ,  C30B15/00 ,  C30B15/203 ,  C30B15/206 ,  C30B15/22 ,  C30B29/06 ,  C30B31/02 ,  C30B31/04 ,  C30B31/165 ,  C30B33/00 ,  H01L21/0201 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/3225 ,  H01L21/76224 ,  H01L29/365 ,  H01L29/78

Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

公开(公告)号：US20180019144A1

公开(公告)日：2018-01-18

申请号：US15645137

申请日：2017-07-10

Applicant: CoorsTek KK

Inventor： Takeshi OGITSU

IPC: H01L21/673 ,  C23C16/458 ,  H01L21/02

CPC classification number: H01L21/67309 ,  C23C16/4583 ,  H01L21/0201 ,  H01L21/02035

Abstract: A vertical wafer boat includes a plurality of struts formed with a shelf plate portion configured to mount a silicon wafer, and a top plate and a bottom plate which fix upper and lower ends of the struts. The shelf plate portion is inclined downward toward the center of the boat, and a wafer support portion which protrudes upward and abuts on an edge portion of the silicon wafer is formed at a distal end of the shelf plate portion. To obtain the vertical wafer boat which supports a silicon wafer to be processed by a shelf plate portion provided in multiple stages, the vertical wafer boat being capable of reducing a risk of contact between a warped outer peripheral portion of a wafer and the shelf plate portion and suppressing deflection of the silicon wafer even when the silicon wafer has a large diameter.