公开(公告)号：US20150262864A1

公开(公告)日：2015-09-17

申请号：US14433061

申请日：2013-08-20

Applicant: NEC CORPORATION

Inventor： Koichiro Okamoto ,  Munehiro Tada ,  Hiromitsu Hada ,  Toshitsugu Sakamoto

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76879 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1675 ,  H01L2221/1036

Abstract: The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.

Abstract translation: 本发明解决了抑制中毒气体的发展以消除布线图案分辨率故障的问题，从而形成所需的布线层结构以提供具有改进的性能产量的功能元件。 用于在半导体衬底上形成多层铜互连的方法包括：形成多层抗蚀剂结构，以在包括层间绝缘膜的衬底上形成给定的抗蚀剂图案，所述层间绝缘膜具有在其部分形成并填充有SOC的通孔 层，所述多层抗蚀剂结构体包含SOC层，SOG层，SiO 2层和从所述基板侧依次叠加的化学放大型抗蚀剂; 使用抗蚀剂图案作为掩模进行蚀刻以形成用于布线层和经由插塞的图案; 并以图案形成布线层和通孔塞。

公开(公告)号：US20150228683A1

公开(公告)日：2015-08-13

申请号：US14618937

申请日：2015-02-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Aiko Kato ,  Yu Nishimura ,  Hiroaki Naruse ,  Keita Torii

IPC: H01L27/146 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14638 ,  H01L27/14687 ,  H01L2221/1036

Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.

Abstract translation: 半导体器件制造方法包括在第一导电构件上形成到达第一绝缘层的孔的步骤; 形成到达第二绝缘层并与孔连通的沟槽的步骤; 形成在孔中露出第一导电构件的开口的步骤; 以及通过在开口，孔和沟槽中嵌入导电材料来形成连接到第一导电构件的第二导电构件的步骤。 在蚀刻条件下形成沟槽，使得相对于第二绝缘层的蚀刻速率低于相对于第三绝缘层的蚀刻速率。

公开(公告)号：US08936829B2

公开(公告)日：2015-01-20

申请号：US12864606

申请日：2009-01-19

Applicant: Hiraku Ishikawa

Inventor： Hiraku Ishikawa

IPC: C23C16/56 ,  H01L21/314 ,  C23C16/26 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/3146 ,  C23C16/26 ,  C23C16/56 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76835 ,  H01L2221/1036

Abstract: Functional groups on the outermost surface of an amorphous hydrocarbon film are substituted. The amorphous hydrocarbon film is formed on a silicon substrate Sub, which is coated with a low-k film. A heat treatment is performed on the amorphous hydrocarbon film in a non-silane gas atmosphere. Next, a heat treatment is performed on the amorphous hydrocarbon film in a silane gas atmosphere immediately after the heat treatment in a non-silane gas atmosphere. After the heat treatment, a film, such as a hard mask, is formed.

Abstract translation: 取代无定形烃膜的最外表面上的官能团。 无定形烃膜形成在涂覆有低k膜的硅衬底Sub上。 在非硅烷气体气氛中对无定形烃膜进行热处理。 接下来，在非硅烷气体气氛中的热处理后立即对硅烷气体气氛中的无定形烃膜进行热处理。 在热处理之后，形成诸如硬掩模的膜。

公开(公告)号：US08759222B2

公开(公告)日：2014-06-24

申请号：US11680709

申请日：2007-03-01

Applicant: Tsutomu Shimayama ,  Takatoshi Kameshima ,  Masaki Okamoto

Inventor： Tsutomu Shimayama ,  Takatoshi Kameshima ,  Masaki Okamoto

IPC: H01L21/311

CPC classification number: H01L21/7682 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  H01L2221/1047

Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.

Abstract translation: 本发明公开了一种制造半导体器件的方法，该方法包括用具有无机材料的骨架结构的叠层结构中的双层绝缘膜涂覆基板的第一步骤，以及将绝缘膜的上层蚀刻到远处的第二步骤 作为绝缘膜的下层。 在半导体器件的制造方法中，第一步是以骨架结构与烃化合物的成孔材料结合的方式进行，使得一层绝缘膜含有比另一层更多的碳 绝缘膜。

公开(公告)号：US20140061913A1

公开(公告)日：2014-03-06

申请号：US13596893

申请日：2012-08-28

Applicant: Ching-Fu Yeh ,  Hsiang-Huan Lee

Inventor： Ching-Fu Yeh ,  Hsiang-Huan Lee

IPC: H01L23/485 ,  H01L21/283

CPC classification number: H01L21/76883 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.

Abstract translation: 铝互连装置包括在基板上形成的金属结构，其中金属结构由铜和铝合金形成，形成在金属结构下方的第一合金层和形成在第一合金层下面的第一势垒层，其中第一 在热处理期间通过第一合金层和相邻电介质层之间的反应产生阻挡层。

公开(公告)号：US20130334700A1

公开(公告)日：2013-12-19

申请号：US13526640

申请日：2012-06-19

Applicant: Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L23/48 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract translation: 一种形成用于半导体器件的双镶嵌金属互连的方法。 该方法包括形成低k电介质层，通过低k电介质层形成通孔，沉积牺牲层，通过牺牲层形成沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积 极低k电介质层填充沟槽之间。 该方法允许形成用于第二级双镶嵌结构的极低k电介质层，同时通过沟槽蚀刻和沟槽金属沉积等工艺避免对该层的损伤。 该方法具有避免通孔级电介质和沟槽级电介质之间的蚀刻停止层的额外优点。

公开(公告)号：US08507377B2

公开(公告)日：2013-08-13

申请号：US12764210

申请日：2010-04-21

Applicant: Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC: H01L21/4763

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.

Abstract translation: 一种制造半导体器件的方法，包括形成有集成电路的集成电路部分和包括围绕所述集成电路部分的金属膜的主壁部分的步骤包括以下步骤：在集成电路部分之间选择性地形成包括金属膜的副壁部分 电路部分和主壁部分，并联形成集成电路部分和主壁部分。 在主壁部的每个角部和所得到的半导体器件的集成电路部分之间设置有“L”形的副壁部。

公开(公告)号：US08273667B2

公开(公告)日：2012-09-25

申请号：US12906434

申请日：2010-10-18

Applicant: Chang Soo Park

Inventor： Chang Soo Park

IPC: H01L21/31

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76835 ,  H01L2221/1036 ,  H01L2221/1047

Abstract: The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.

Abstract translation: 本发明涉及半导体器件的制造方法。 更具体地，该方法描述了如何制造具有形成在金属线之间的多孔，低介电常数层的半导体器件，其包括绝缘层包封填料。

公开(公告)号：US20110108987A1

公开(公告)日：2011-05-12

申请号：US12897941

申请日：2010-10-05

Applicant: Hideyuki Tomizawa ,  Tadayoshi Watanabe ,  Noriaki Matsunaga

Inventor： Hideyuki Tomizawa ,  Tadayoshi Watanabe ,  Noriaki Matsunaga

IPC: H01L23/532

CPC classification number: H01L23/485 ,  H01L21/76807 ,  H01L21/76846 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, may include a first insulating layer formed on a semiconductor substrate, a contact provided in the first insulating layer, a second dielectric layer formed on the first insulating layer, the second insulating layer having lower dielectric constant than the first dielectric layer, a wiring formed in the second insulating layer and being electrically connected to the contact, a first barrier metal formed on a bottom of the contact and on a side surface of the wiring, and a second barrier metal formed on a side surface of the bottom and on the first barrier metal.

Abstract translation: 半导体器件可以包括形成在半导体衬底上的第一绝缘层，设置在第一绝缘层中的触点，形成在第一绝缘层上的第二绝缘层，第二绝缘层的介电常数比第一绝缘层低， 形成在第二绝缘层中并且与触点电连接的布线，形成在触点的底部上和布线的侧表面上的第一阻挡金属和形成在底部的侧表面上的第二阻挡金属， 在第一个屏障金属上。

公开(公告)号：US07932176B2

公开(公告)日：2011-04-26

申请号：US12408473

申请日：2009-03-20

Applicant: Roy Gerald Gordon ,  Hoon Kim

Inventor： Roy Gerald Gordon ,  Hoon Kim

IPC: H01L21/4763

CPC classification number: H01L21/76864 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract translation: 用于集成电路的互连结构包括在集成电路中完全包围铜线的硅酸锰和锰氮化硅层，以及用于制造其的方法。 硅酸锰形成阻止铜从电线扩散的屏障，从而保护绝缘体不被过早击穿，并保护晶体管免受铜的退化。 硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。 铜锰硅酸盐和锰氮化硅界面的强粘附性也可防止在使用设备期间铜的电迁移而导致故障。 含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。