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    CHIP X2 CORRELATION HYPOTHESES USING CHIP X1 SAMPLES
    12.
    发明申请
    CHIP X2 CORRELATION HYPOTHESES USING CHIP X1 SAMPLES 审中-公开
    使用芯片X1样品的芯片X2相关假设

    公开(公告)号：US20130028296A1

    公开(公告)日：2013-01-31

    申请号：US13192003

    申请日：2011-07-27

    Applicant: Aamod D. Khandekar ,  Dario Fertonani ,  Srikanth Gummadi

    Inventor： Aamod D. Khandekar ,  Dario Fertonani ,  Srikanth Gummadi

    IPC: H04B1/707

    CPC classification number: H04B1/7075 ,  H04B2001/70724 ,  H04B2201/70707 ,  H04B2201/70713 ,  H04B2201/70727

    Abstract: A UE may store received samples of a wireless signal at cx1 to reduce memory usage, but then may correlate those samples with cx2 timing hypotheses to improve performance. The received sequence is resampled at cx2 instead of cx1. The UE still performs the correlation of the cx2 timing hypotheses for the performance gain, but the reference waveform is resampled with cx2 time offset. A Fast Fourier Transform (FFT) may be taken of the received and reference waveforms. In the frequency domain, resampling may be performed by multiplying the FFT of the reference waveform by a phase ramp—a pointwise multiplication in the frequency domain with a constant magnitude sequence whose phase varies linearly.

    Abstract translation: UE可以以cx1存储无线信号的接收样本以减少存储器使用，但是然后可以将这些采样与cx2定时假设相关联以提高性能。 接收的序列在cx2而不是cx1重采样。 UE仍然执行cx2定时假设与性能增益的相关性，但参考波形用cx2时间偏移重采样。 可以对接收和参考波形进行快速傅里叶变换（FFT）。 在频域中，重采样可以通过将参考波形的FFT乘以频域中的相位斜坡 - 点相乘乘以其相位线性变化的恒定幅度序列来执行。

    Interface between chip rate processing and bit rate processing in wireless downlink receiver
    13.
    发明授权
    Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
    无线下行接收机芯片速率处理与比特率处理之间的接口

    公开(公告)号：US08358988B2

    公开(公告)日：2013-01-22

    申请号：US11529146

    申请日：2006-09-28

    Applicant: Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    Inventor： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    IPC: H04B1/18

    CPC classification number: H04B1/7105 ,  H04B2201/70707

    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

    Abstract translation: 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级 并且提供编码的传输信道数据。 后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

    Correlation Device
    14.
    发明申请
    Correlation Device 有权
    相关设备

    公开(公告)号：US20130013660A1

    公开(公告)日：2013-01-10

    申请号：US13551144

    申请日：2012-07-17

    Applicant: Tilo Ferchland ,  Frank Poegel ,  Eric Sachse

    Inventor： Tilo Ferchland ,  Frank Poegel ,  Eric Sachse

    IPC: G06F17/15

    CPC classification number: H04B1/707 ,  G06F17/15 ,  H04B2201/70707 ,  H04L7/042 ,  H04L7/043 ,  H04L7/08

    Abstract: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition signal sequence coefficient with a linking coefficient to obtain a correlation result.

    Abstract translation: 提供了一种相关装置，其包括用于将输入信号序列和辅助信号序列相加以获得加法信号序列的加法器和用于延迟加法信号序列以获得辅助信号序列的延迟元件，由此延迟元件具有 多个系数输出用于提供加法信号序列系数。 相关装置还包括用于将加法信号序列系数与连接系数进行系数连接以获得相关结果的链接元件。

    Blind detection of the transport format (TF) of a signal
    16.
    发明授权
    Blind detection of the transport format (TF) of a signal 有权
    信号的传输格式（TF）的盲检测

    公开(公告)号：US08315344B2

    公开(公告)日：2012-11-20

    申请号：US12421059

    申请日：2009-04-09

    Applicant: Markus Ringström ,  Pär Moqvist ,  Yi-Pin Eric Wang

    Inventor： Markus Ringström ,  Pär Moqvist ,  Yi-Pin Eric Wang

    IPC: H04B1/10

    CPC classification number: H04B1/7103 ,  H04B2201/70705 ,  H04B2201/70707 ,  H04W24/00

    Abstract: The transport format (TF) of a signal may be blindly detected from a reduced set of TF hypotheses. In an example embodiment, a method for the blind detection of a TF of a signal includes filtering a set of transport format hypotheses to identify a reduced set of TF hypotheses using one or more filtering schemes. From the reduced set of TF hypotheses, a TF that is associated with an interfering signal is detected. The TF includes a modulation and a spreading factor for the interfering signal. It may also include a number of channelization codes. In an example implementation, when an interfering signal is to be canceled, symbols carried by the signal are detected using the detected TF. Example filtering schemes include filtering based on system design/operation, filtering based on known configuration information, filtering based on an expected level of interference contribution, and so forth.

    Abstract translation: 信号的传输格式（TF）可以从减少的一组TF假设中盲目地检测出来。 在示例实施例中，用于盲检测信号的TF的方法包括：使用一个或多个过滤方案来过滤一组传输格式假设以识别减少的TF假设集合。 从减少的TF假设集合中，检测到与干扰信号相关联的TF。 TF包括用于干扰信号的调制和扩频因子。 它还可以包括多个信道化码。 在示例实现中，当要消除干扰信号时，使用检测到的TF检测由信号携带的符号。 示例性过滤方案包括基于系统设计/操作的过滤，基于已知配置信息的过滤，基于预期干扰贡献水平的过滤等等。

    Adaptive code generator for satellite navigation receivers
    17.
    发明授权
    Adaptive code generator for satellite navigation receivers 有权
    用于卫星导航接收机的自适应码发生器

    公开(公告)号：US08243772B2

    公开(公告)日：2012-08-14

    申请号：US12955823

    申请日：2010-11-29

    Applicant: Jerry Eugene Knight ,  Charles R. Cahn ,  David Man Kui Li

    Inventor： Jerry Eugene Knight ,  Charles R. Cahn ,  David Man Kui Li

    IPC: H04B1/00

    CPC classification number: H04B1/707 ,  G01S19/30 ,  G01S19/33 ,  G01S19/37 ,  H04B2201/70707 ,  H04B2201/70715 ,  H04J13/00 ,  H04J13/10

    Abstract: An adjustable code generator is configurable to generate any of a plurality of spread-spectrum code signals. The adjustable code generator includes a feedback polynomial mask table to contain a set of feedback polynomial masks. Respective feedback polynomial masks of the set correspond to respective spread-spectrum code signals of the plurality of spread-spectrum code signals. The adjustable code generator also includes control logic to select any of the feedback polynomial masks of the set contained in the feedback polynomial mask table, and further includes a shift register to provide, at an output, a respective spread-spectrum code signal that corresponds to a feedback polynomial mask selected by the control logic and to receive feedback generated using the feedback polynomial mask selected by the control logic.

    Abstract translation: 可调节码发生器可配置为产生多个扩频码信号中的任何一个。 可调节代码生成器包括反馈多项式掩码表以包含一组反馈多项式掩码。 该集合的相应反馈多项式掩码对应于多个扩频码信号的各个扩频码信号。 可调码生成器还包括控制逻辑，用于选择反馈多项式掩码表中包含的集合的反馈多项式掩模中的任何一个，并且还包括移位寄存器，用于在输出端提供对应于 由控制逻辑选择的反馈多项式掩模，并接收使用由控制逻辑选择的反馈多项式掩码产生的反馈。

    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER
    18.
    发明申请
    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER 审中-公开
    用于降低芯片级均衡接收机的处理速率的方法和装置

    公开(公告)号：US20120195358A1

    公开(公告)日：2012-08-02

    申请号：US13439350

    申请日：2012-04-04

    Applicant: Jung-Lin Pan

    Inventor： Jung-Lin Pan

    IPC: H04L27/01 ,  H04B1/06

    CPC classification number: H04B1/70757 ,  H04B1/707 ,  H04B1/7115 ,  H04B2201/70707 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03617

    Abstract: A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

    Abstract translation: 一种用于在包括均衡器滤波器的码分多址（CDMA）接收机中执行码片级均衡（CLE）时降低处理速率的方法和装置。 由接收机的至少一个天线接收的信号以芯片速率的M倍采样。 每个样本流以码片速率被分成M个采样数据流。 优选对每个分割样本数据流执行多路径组合。 然后将样本数据流以码片速率组合成一个组合的采样数据流。 均衡器滤波器以码片速率对组合的采样流进行均衡。 通过将校正项加到由均衡器滤波器用于先前迭代的滤波器系数来调整滤波器系数。

    Multistage PN code acquisition circuit and method
    20.
    发明授权
    Multistage PN code acquisition circuit and method 有权
    多级PN码采集电路及方法

    公开(公告)号：US08126092B2

    公开(公告)日：2012-02-28

    申请号：US10918839

    申请日：2004-08-13

    Applicant: Sundararajan Sriram ,  Srinath Hosur

    Inventor： Sundararajan Sriram ,  Srinath Hosur

    IPC: H04L27/06

    CPC classification number: H04B1/70752 ,  H04B1/70735 ,  H04B1/7077 ,  H04B1/7093 ,  H04B2201/70702 ,  H04B2201/70707

    Abstract: A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code. The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of timer periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

    Abstract translation: 用于检测串行信号的电路包括第一电路，其耦合以在基本相等的持续时间的预定多个时间段内接收串行信号。 第一电路被耦合以接收第一代码。 第一电路被布置为将与多个定时器周期的每个时间段相对应的一部分串行信号与第一代码进行比较，从而产生匹配信号。 第一电路从多个时间段的每个时间段的每一个累加匹配信号。

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