公开(公告)号：US07667331B2

公开(公告)日：2010-02-23

申请号：US12217643

申请日：2008-07-08

Applicant: Jong-Seok Lim ,  Hyo-Dong Ban

Inventor： Jong-Seok Lim ,  Hyo-Dong Ban

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/585 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4911 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01083 ,  H01L2924/19107 ,  H01L2924/30105 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An interposer chip in accordance includes an insulating layer, conductive patterns and a dummy pattern. The conductive patterns are formed on the insulating layer. The dummy pattern is formed on the insulating layer to suppress a bending of the insulating layer. Further, the dummy pattern can have first isolating grooves formed along peripherals of the conductive patterns to isolate the dummy pattern from the conductive patterns. Thus, the interposer chip is not vulnerable to being bent. Further, an electrical short between the conductive patterns through the dummy pattern caused by particles is substantially avoided.

Abstract translation: 根据绝缘层，导电图案和虚拟图案，插入器芯片。 导电图案形成在绝缘层上。 在绝缘层上形成虚设图形以抑制绝缘层的弯曲。 此外，虚设图案可以具有沿着导电图案的外围形成的第一隔离槽，以将虚设图案与导电图案隔离。 因此，插入器芯片不易弯曲。 此外，基本上避免了通过由颗粒引起的虚拟图案的导电图案之间的电短路。

公开(公告)号：US20090237889A1

公开(公告)日：2009-09-24

申请号：US12411225

申请日：2009-03-25

Applicant: Jason Walter Swanson ,  Bryan Wayne McCoy ,  Arthur Kenneth Dewyer

Inventor： Jason Walter Swanson ,  Bryan Wayne McCoy ,  Arthur Kenneth Dewyer

IPC: H05K7/20

CPC classification number: H05K1/0206 ,  H05K1/0209 ,  H05K1/0298 ,  H05K2201/09363 ,  H05K2201/09781

Abstract: A power converter including a printed circuit board (PCB) having a plurality of heat conductive layers configured to sink heat generated by the power converter electronics. Each of these heat conductive layers are comprised of thermally conductive material configured as planar sheets, each of these heat conductive layers being coupled to at least one wire to sink heat therefrom, such as via a wire of an input cable and/or output cable. Advantageously, a more compact power converter is realized having improved power output while operating within safety guidelines.

Abstract translation: 一种功率转换器，包括具有多个导热层的印刷电路板（PCB），所述导热层被配置为吸收由所述功率转换器电子器件产生的热量。 这些导热层中的每一个由配置为平面片的导热材料构成，这些导热层中的每一个都耦合到至少一根导线，从而通过输入电缆和/或输出电缆的导线吸收热量。 有利地，在安全准则下操作时，实现了具有改进的功率输出的更紧凑的功率转换器。

公开(公告)号：US07572031B2

公开(公告)日：2009-08-11

申请号：US11669622

申请日：2007-01-31

Applicant: John C. Schultz ,  Andrew J Ouderkirk ,  Joel S. Peiffer ,  Nelson B. O'Bryan ,  John A. Wheatley ,  Cameron T. Murray

Inventor： John C. Schultz ,  Andrew J Ouderkirk ,  Joel S. Peiffer ,  Nelson B. O'Bryan ,  John A. Wheatley ,  Cameron T. Murray

IPC: F21V33/00

CPC classification number: H05K1/189 ,  F21K9/00 ,  G02F1/133603 ,  G02F2001/133628 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/3011 ,  H05K1/0203 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/0061 ,  H05K3/386 ,  H05K2201/0209 ,  H05K2201/091 ,  H05K2201/09363 ,  H05K2201/10106 ,  Y10S362/80 ,  H01L2924/00 ,  H01L2224/4554

Abstract: An illumination assembly includes a compliant substrate comprising a first and second electrically conductive foil separated by an electrically insulating layer. The insulating layer includes a polymer material loaded with particles that enhance thermal conductivity of the insulating layer. A plurality of LED dies are disposed on the first conductive foil.

Abstract translation: 照明组件包括柔性衬底，其包括由电绝缘层分隔开的第一和第二导电箔。 绝缘层包括装载有增强绝缘层导热性的颗粒的聚合物材料。 多个LED管芯设置在第一导电箔上。

公开(公告)号：US20060046569A1

公开(公告)日：2006-03-02

申请号：US11069946

申请日：2005-03-03

Applicant: Takahiro Kondou ,  Mitsuru Kobayashi

Inventor： Takahiro Kondou ,  Mitsuru Kobayashi

IPC: H01R13/648

CPC classification number: H01R9/034 ,  H01R9/032 ,  H01R13/6471 ,  H01R13/6585 ,  H01R13/6592 ,  H01R24/562 ,  H01R2107/00 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09363

Abstract: A disclosed balanced transmission cable connector includes a relay board having a wiring pattern extending from the upper face to the lower face through a via hole. Wire connection pads to output signals are disposed on the upper face of the relay board, and wire connection pads to input signals are disposed on the lower face of the relay board. Two wires of a pair wire are soldered to the wire connection pads disposed on the same face of the relay board. A ground layer inside the relay board shields between the soldered parts of the pair wire to transmit output signals and the soldered parts of the pair wire to transmit input signals.

公开(公告)号：US20060003481A1

公开(公告)日：2006-01-05

申请号：US11216959

申请日：2005-08-31

Applicant: Warren Farnworth ,  Alan Wood

Inventor： Warren Farnworth ,  Alan Wood

IPC: H01L21/00 ,  H01L29/06

CPC classification number: H01L23/3128 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0218 ,  H05K1/113 ,  H05K3/027 ,  H05K2201/09363 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.

公开(公告)号：US5733466A

公开(公告)日：1998-03-31

申请号：US596052

申请日：1996-02-06

Applicant: Biebele Opubo Benebo ,  Edmund Glenn Benjamin ,  Robert Douglas Edwards ,  John Joseph Konrad ,  Timothy Leroy Wells ,  Jerzy Maria Zalesinski

Inventor： Biebele Opubo Benebo ,  Edmund Glenn Benjamin ,  Robert Douglas Edwards ,  John Joseph Konrad ,  Timothy Leroy Wells ,  Jerzy Maria Zalesinski

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  B44C1/22

CPC classification number: H05K3/242 ,  H05K3/243 ,  H05K2201/09363 ,  H05K2203/0542 ,  H05K2203/1476 ,  H05K3/064 ,  H05K3/108

Abstract: Electrodepositing a metallurgy such as gold on to printed circuit board features. The methods include electrolessly depositing a copper layer over the surface of the printed circuit board. This is followed by applying a layer of photoresist atop the electroless copper, and exposing and developing the photoresist to uncover areas to be etched, leaving behind the specific features to be plated. By this expedient the remaining copper forms a commoning layer. The remaining photoresist is stripped to uncover the copper commoning layer, and a second layer of photoresist is applied atop the partially etched copper layer. This layer of photoresist is exposed and developed to uncover the features to be plated. These features are then plated with the metallurgy of choice. The photoresist is then stripped off and the electroless copper layer can remain if needed for further processing or be microetched off without harming copper traces that may exist below the electroless copper layer.

Abstract translation: 将诸如金的冶金电沉积到印刷电路板的特征上。 所述方法包括在印刷电路板的表面上无电沉积铜层。 然后在化学镀铜的顶部涂上一层光致抗蚀剂，然后曝光和显影光致抗蚀剂以露出要蚀刻的区域，留下要镀覆的特定特征。 通过这种方式，剩余的铜形成共同的层。 将剩余的光致抗蚀剂剥离以露出铜共同层，并且将第二层光致抗蚀剂施加在部分蚀刻的铜层上。 该层光致抗蚀剂被曝光和显影以露出要镀覆的特征。 然后将这些特征镀上所选择的冶金。 然后剥离光致抗蚀剂，如果需要进一步处理，则可以保留化学镀铜层，或者在不损害无电镀铜层下方的铜迹线的情况下进行微蚀刻。

公开(公告)号：US5457593A

公开(公告)日：1995-10-10

申请号：US166230

申请日：1993-12-13

Applicant: James A. Glaser ,  Ronald W. Glaser

Inventor： James A. Glaser ,  Ronald W. Glaser

IPC: H01R9/24 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/22 ,  H02H9/00

CPC classification number: H05K1/0265 ,  H01R9/24 ,  H05K1/0257 ,  H01R9/2441 ,  H04Q2201/12 ,  H05K1/0287 ,  H05K1/18 ,  H05K2201/09363 ,  H05K2201/09445 ,  H05K2201/09609 ,  H05K2201/10287 ,  H05K2201/10325 ,  H05K3/222

Abstract: A protector block assembly for coupling a plurality of surge protectors to multi-line telecommunications cables includes a multi-layer printed circuit, to which has been mounted at least two cable connectors, and a protector block having a plurality of sockets for receiving standard surge protectors. A plurality of pins electrically and physically connects the multi-layer printed circuit board to the sockets on the protector block in a manner that a unique signal path exists between each lead in each connector and one of the sockets on the printed circuit board. The multi-layer printed circuit board includes traces on multiple layers that have a width and a copper content sufficient to carry current surges without breaking down.

Abstract translation: 用于将多个浪涌保护器耦合到多线电信电缆的保护器块组件包括已经安装有至少两个电缆连接器的多层印刷电路，以及具有用于接收标准浪涌保护器的多个插座的保护器块 。 多个引脚将多层印刷电路板电气和物理地连接到保护器块上的插座，使得在每个连接器中的每个引线与印刷电路板上的插座中的一个之间存在唯一的信号路径。 多层印刷电路板包括具有宽度和铜含量的多层迹线，足以承载电流而不破坏。

公开(公告)号：US09799807B2

公开(公告)日：2017-10-24

申请号：US15417373

申请日：2017-01-27

Applicant: NICHIA CORPORATION

Inventor： Motokazu Yamada ,  Tadaaki Miyata ,  Naoki Mori

IPC: H01L33/56 ,  H01L25/075 ,  H01L33/32 ,  H01L33/48 ,  H01L33/50 ,  H01L33/60 ,  H01L33/62 ,  F21S4/22 ,  F21Y103/00

CPC classification number: H01L33/56 ,  F21S4/22 ,  F21Y2101/00 ,  F21Y2103/00 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/32 ,  H01L33/483 ,  H01L33/507 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: A light emitting device includes a substrate, a light emitting element and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions and a groove portion. The groove portion is formed between the plurality of wiring portions spaced apart from each other, and includes a first groove portion, a second groove portion, and a third groove portion extending in a direction intersecting the first and second groove portions. The first and third groove portions are connected to each other with a curve. The second and third groove portions are connected to each other with a curve. The sealing resin member seals the light emitting element and the substrate. The sealing resin member is arranged on the third groove portion and spaced apart from the first groove portion and the second groove portion.

公开(公告)号：US09590152B2

公开(公告)日：2017-03-07

申请号：US14956804

申请日：2015-12-02

Applicant: NICHIA CORPORATION

Inventor： Motokazu Yamada ,  Tadaaki Miyata ,  Naoki Mori

IPC: H01L33/56 ,  H01L33/54 ,  H01L33/48 ,  H05K1/18 ,  H01L33/62 ,  H01L27/15 ,  H01L33/60 ,  H01L33/32 ,  H01L33/50 ,  H01L25/075 ,  H05K1/11 ,  F21Y101/00

CPC classification number: H01L33/56 ,  F21S4/22 ,  F21Y2101/00 ,  F21Y2103/00 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/32 ,  H01L33/483 ,  H01L33/507 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: A light emitting device includes a substrate, a light emitting device and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions, a groove portion and a pair of terminal portions. The flexible base extends in a first direction corresponding to a longitudinal direction of the substrate and the plurality of wiring portions are arranged on the flexible base. The groove portion is formed between the plurality of wiring portions spaced apart from each other. The pair of terminal portions is arranged along the first direction at the both sides of the plurality of wiring portions. The light emitting element is disposed on the substrate and electrically connected to the plurality of wiring portions. The sealing resin member seals the light emitting element and a part of the substrate. The light emitting element is mounted on the substrate in a flip-chip manner.

Abstract translation: 发光器件包括衬底，发光器件和密封树脂构件。 基板包括柔性基座，多个布线部分，槽部分和一对端子部分。 柔性基部沿着与基板的纵向相对应的第一方向延伸，并且多个布线部布置在柔性基部上。 槽部形成在彼此间隔开的多个配线部之间。 一对端子部分沿着第一方向布置在多个布线部分的两侧。 发光元件设置在基板上并电连接到多个布线部分。 密封树脂构件密封发光元件和基板的一部分。 发光元件以倒装芯片方式安装在基板上。

公开(公告)号：US09414499B2

公开(公告)日：2016-08-09

申请号：US13695870

申请日：2011-03-23

Applicant: Jan van Aalst ,  Drago Kovacic ,  Bostjan Podobnik

Inventor： Jan van Aalst ,  Drago Kovacic ,  Bostjan Podobnik

IPC: H05K3/02 ,  B23K26/36

CPC classification number: H05K3/027 ,  B23K26/36 ,  B23K2101/38 ,  H05K2201/062 ,  H05K2201/09363

Abstract: A method for partial detachment of a defined area of a conductive layer using a laser beam includes forming a conductor track with a defined path from the conductive layer on the substrate, the path defining main axes. The area is segmented into zones. A linear recess is provided along a respective perimeter of each of the zones. Each of the zones has a strip shape such that the recesses extend along paths that are substantially straight lines not parallel to either of the main axes. One of the zones to be removed is heated using laser radiation until adhesion of the conductive layer to the substrate is substantially reduced and the zone to be removed is detached in a surface-wide manner from the substrate under external influences. Laser-beam parameters are set such that only the conductive layer is removed without affecting an underlying substrate.

Abstract translation: 使用激光束对导电层的限定区域进行部分分离的方法包括从基板上的导电层形成具有限定路径的导体轨迹，该路径限定主轴。 该区域被分割成区域。 沿着每个区域的相应周边设置有线性凹槽。 每个区域具有带状，使得凹部沿着不平行于任一主轴线的基本直线的路径延伸。 使用激光辐射来加热待除去的区域之一，直到导电层与基底的粘合性大大降低，并且在外部影响下将被去除的区域以表面宽度的方式与基底分离。 激光束参数被设置为使得仅去除导电层而不影响下面的衬底。