公开(公告)号：US5805838A

公开(公告)日：1998-09-08

申请号：US655999

申请日：1996-05-31

Applicant: Ivan E. Sutherland ,  Lee S. Tavrow

Inventor： Ivan E. Sutherland ,  Lee S. Tavrow

IPC: G06F12/00 ,  G06F9/48 ,  G06F13/364 ,  H01J13/00

CPC classification number: G06F13/364

Abstract: Improved circuits for implementing various embodiments of high performance arbiters are disclosed. In one embodiment, a late-done arbiter is implemented by combining a late-decision arbiter with a decision storage (or queue) device. In another embodiment, an arbiter implementation that extends the amount of storage available for decisions is disclosed. A decision making device such as a simple arbiter is followed by a decision storage device such as a queue or a first in first out (FIFO) register of any number of stages. The decision storage device following the arbiter allows the arbiter to report each decision as quickly as it can and to start the next decision making cycle.

Abstract translation: 公开了用于实现高性能仲裁器的各种实施例的改进电路。 在一个实施例中，通过将后期决策仲裁器与决策存储（或队列）设备组合来实现后期完成的仲裁器。 在另一个实施例中，公开了延长可用于决定的存储量的仲裁器实现。 诸如简单仲裁器的决策设备之后是诸如队列或任何级数的先进先出（FIFO）寄存器的决策存储设备。 遵循仲裁器的决策存储设备允许仲裁者尽可能快地报告每个决策，并开始下一个决策循环。

公开(公告)号：US5796494A

公开(公告)日：1998-08-18

申请号：US452564

申请日：1995-05-25

Applicant: Yuji Asano

Inventor： Yuji Asano

IPC: G06F13/00 ,  H04N1/00 ,  H04N1/23 ,  H04N1/32 ,  H01J13/00 ,  H04N1/40

CPC classification number: H04N1/00238 ,  H04N1/00206 ,  H04N1/00236 ,  H04N2201/0074

Abstract: A facsimile machine including a first facsimile-data receiver including a connector connectable to an external computer for receiving, from the computer, facsimile data including image data representing an image, and receiver-designating data designating a second facsimile-data receiver to which the facsimile data are transmitted, a facsimile-data transmitter which transmits the facsimile data to the second facsimile-data receiver designated by the receiver-designating data, a recorder which records, on a recording medium, the image represented by the image data of the facsimile data, a memory which stores self-designating data designating the first facsimile-data receiver, the receiver-designating data and the self-designating data being of same kind of data as each other, so that the receiver-designating data are comparable with the self-designating data, and a control device which controls the recorder to record the image represented by the image data when the receiver-designating data are identical with the self-designating data, and does not control the recorder to record the image when the receiver-designating data are not identical with the self-designating data.

Abstract translation: 一种传真机，包括第一传真数据接收机，其包括可连接到外部计算机的连接器，用于从计算机接收包括表示图像的图像数据的传真数据，以及指定传真数据接收器的接收机指定数据 发送数据，将传真数据发送到由接收方指定数据指定的第二传真数据接收器的传真数据发送器，在记录介质上记录由传真数据的图像数据表示的图像的记录器 存储器，其存储指定第一传真数据接收器的指定数据，接收器指定数据和彼此相同类型数据的自指定数据，使得接收器指定数据与自身相当 指定数据，以及控制装置，其控制记录器，以在接收器指定时记录由图像数据表示的图像 ata与自我指定数据相同，并且当接收机指定数据与自指定数据不相同时，不控制记录器记录图像。

公开(公告)号：US5793994A

公开(公告)日：1998-08-11

申请号：US594868

申请日：1996-01-31

Applicant: Bruce W. Mitchell ,  James S. H. Cho ,  Greg Walter ,  John H. Hughes ,  Roger D. Rothhaar

Inventor： Bruce W. Mitchell ,  James S. H. Cho ,  Greg Walter ,  John H. Hughes ,  Roger D. Rothhaar

IPC: G06F13/42 ,  H01J13/00

CPC classification number: G06F13/4234

Abstract: A bus protocol technique removes the transaction used for posting indications of events to the host processor from the bus. The invention takes advantage of the fact that addresses typically on a high speed bus contain fewer bits than the entire bus width. Particularly, for a 32 bit bus, the 32 bit address space is not always necessary. The remaining bits on the bus are used for an encoded event tag. A bus transaction involves a first bus transfer which provides an address for writing or reading data, along with the event tag. The event tag is detected and decoded by the destination, and the event is posted to the processor which monitors and responds to events, in a manner which is synchronous with completion of the transaction. Thus, after the transaction on the bus, the message subject of the transaction is waiting in the memory, and notification of the event has occurred automatically and synchronously with completion of the transfer.

Abstract translation: 总线协议技术从总线中去除用于向主机处理器发布事件的事件的事务。 本发明利用了这样的事实，即通常在高速总线上的地址比整个总线宽度包含更少的位。 特别地，对于32位总线，32位地址空间并不总是必需的。 总线上的其余位用于编码事件标签。 总线事务涉及第一个总线传输，其提供写入或读取数据的地址以及事件标签。 由目的地检测和解码事件标签，并且以与事务完成同步的方式将事件发布到监视和响应事件的处理器。 因此，在总线上的交易之后，事务的消息主体正在等待在存储器中，并且事件的通知已经自动并且与传送完成同步地发生。

公开(公告)号：US5787264A

公开(公告)日：1998-07-28

申请号：US437233

申请日：1995-05-08

Applicant: Kevin M. Christiansen ,  Mark A. Stubbs ,  Bruce Eckstein

Inventor： Kevin M. Christiansen ,  Mark A. Stubbs ,  Bruce Eckstein

IPC: G06F13/364 ,  H01J13/00

CPC classification number: G06F13/364

Abstract: The present invention is directed to providing a computer system which arbitrates control of a shared bus among plural devices included in the computer system. In accordance with the present invention, at least one of the devices is afforded a higher priority than the remaining devices, yet none of the remaining devices are effectively denied system bus access or control for extended periods of time. The present invention can therefore increase operating efficiency even as the number of devices included in the computer system is increased to achieve enhanced processing power. In addition, the present invention can provide sophisticated multimedia features, including real time signal processing, without sacrificing overall operating efficiency. In accordance with the present invention, the plural devices arbitrate system bus control in a manner which achieves acceptable multimedia results when processing real time data streams such as video data streams, audio data streams, animation data streams, and so forth, yet which does not sacrifice the access of remaining devices in the computer system to the shared bus.

Abstract translation: 本发明旨在提供一种计算机系统，该计算机系统在包括在计算机系统中的多个设备之中仲裁共享总线的控制。 根据本发明，至少一个设备被提供比其余设备更高的优先级，但是其余设备中的任何一个都不会在延长的时间段内被有效地拒绝系统总线访问或控制。 因此，即使增加计算机系统中包括的设备的数量来增加处理能力，本发明也可以提高运行效率。 此外，本发明可以提供复杂的多媒体特征，包括实时信号处理，而不牺牲总体操作效率。 根据本发明，多个设备在处理诸如视频数据流，音频数据流，动画数据流等等的实时数据流时，以实现可接受的多媒体结果的方式仲裁系统总线控制，但是不 牺牲计算机系统中剩余设备到共享总线的访问。

公开(公告)号：US5774684A

公开(公告)日：1998-06-30

申请号：US730996

申请日：1996-10-08

Applicant: Ralph Warren Haines ,  Dan Craig O'Neill ,  Stephen C. Pries ,  William V. Miller ,  Kent B. Waterson ,  David S. Weinman ,  Michael J. Shay ,  Jianhua Helen Pang ,  Daniel R. Herrington ,  Brian J. Marley ,  John R. Gunther ,  Alexander Perez ,  James Andrew Colgan ,  Robert James Divivier

Inventor： Ralph Warren Haines ,  Dan Craig O'Neill ,  Stephen C. Pries ,  William V. Miller ,  Kent B. Waterson ,  David S. Weinman ,  Michael J. Shay ,  Jianhua Helen Pang ,  Daniel R. Herrington ,  Brian J. Marley ,  John R. Gunther ,  Alexander Perez ,  James Andrew Colgan ,  Robert James Divivier

IPC: G06F11/36 ,  G06F13/368 ,  H01J13/00

CPC classification number: G06F11/3652 ,  G06F13/368

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).

Abstract translation: 集成电路（IC）包括多个电路和功能，它们根据分布式总线访问和控制仲裁共享多个内部信号总线，三个物理和五个逻辑。 多个内部信号总线由三层内部电路功能共享：中央处理单元和DMA控制器; DRAM控制器和总线接口单元; 和外围接口电路，如PCMCIA和显示控制器。 两条物理总线对应于两条逻辑总线，用于IC内的通信。 第三物理总线对应于三条逻辑总线，用于IC和IC外部的电路之间的通信。 用于访问和控制各种信号总线的仲裁分布在三层内部电路功能内部。 因此，从最频繁访问的电路功能可以实现最大性能，同时仍能从较少频繁访问的电路功能中获得高性能。 IC可以提供具有支持在线仿真（ICE）的特征的处理器核心。

公开(公告)号：US5737543A

公开(公告)日：1998-04-07

申请号：US392576

申请日：1995-02-23

Applicant: Derwin DeLon Gavin ,  Daniel Cletus Gillen ,  Jessie Ann Hays Haug ,  James Britt Partridge ,  Lance Warren Russell ,  Eldon Perry Smith

Inventor： Derwin DeLon Gavin ,  Daniel Cletus Gillen ,  Jessie Ann Hays Haug ,  James Britt Partridge ,  Lance Warren Russell ,  Eldon Perry Smith

IPC: G06F13/38 ,  H01J13/00

CPC classification number: G06F13/385

Abstract: A computer system, memory, and computer-implemented method for generating at least one high performance communication path is provided. The communication path has a plurality of linked components, including a negotiator and a controller. The method includes the steps of registering the negotiator with the controller (e.g. stream head), verifying acknowledgement of negotiation from each component linked between the negotiator and the controller, and in response to a valid verification, redirecting I/O between the controller and the negotiator.

Abstract translation: 提供了一种用于产生至少一个高性能通信路径的计算机系统，存储器和计算机实现的方法。 通信路径具有多个链接的部件，包括协商者和控制器。 该方法包括以下步骤：将协商者与控制器（例如流头）注册，验证来自协商者和控制器之间链接的每个组件的协商确认，以及响应于有效验证，重定向控制器与控制器之间的I / O 谈判者

公开(公告)号：US5671374A

公开(公告)日：1997-09-23

申请号：US428692

申请日：1995-04-25

Applicant: Joel R. Postman ,  George B. Miller ,  Ronald C. Fish

Inventor： Joel R. Postman ,  George B. Miller ,  Ronald C. Fish

IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F3/023 ,  G06F3/038 ,  G06K7/00 ,  H01J13/00

CPC classification number: G06F3/038 ,  G06F1/1626 ,  G06F1/1632 ,  G06F3/00 ,  G06F3/002 ,  G06F3/023 ,  G06F3/0383

Abstract: A variety of PC card interfaces to interface from many different types of input devices to Personal Digital Assistants or palmtop computers through PCMCIA slots. The disclosed interfaces can receive data in undecoded format from laser based, wand based or CCD based barcode scanning engines, decode the data to alphanumeric characters and pass the decoded data to the PDA via the PCMCIA 68 pin bus. Other PC card based interfaces are also disclosed which can accept input data in the form of ASCII or EBCDIC characters from virtually any type of input device which a standard serial or parallel output or custom output bus and input that data to the PDA through the PCMCIA bus. Some embodiments use programmed general purpose microprocessors to decode undecoded barcode scan data on the PC card. Other embodiments use custom-programmed, commercially available barcode decoding chips to decode incoming undecoded barcode scan data. Some embodiments of PC card interfaces sample undecoded barcode scan signals and pass the samples to the host through the PCMCIA bus for decoding by a suitably programmed host computer.

Abstract translation: 各种PC卡接口，可通过PCMCIA插槽从多种不同类型的输入设备连接到个人数字助理或掌上电脑。 所公开的接口可以从基于激光的，基于魔杖的或基于CCD的条形码扫描引擎接收未编码格式的数据，将数据解码为字母数字字符，并通过PCMCIA 68引脚总线将解码的数据传送到PDA。 还公开了其他基于PC卡的接口，其可接受来自几乎任何类型的输入设备的ASCII或EBCDIC字符形式的输入数据，标准串行或并行输出或定制输出总线并通过PCMCIA总线将数据输入到PDA 。 一些实施例使用编程的通用微处理器来解码PC卡上未解码的条形码扫描数据。 其他实施例使用自定义编程的市售条形码解码芯片来解码输入未解码的条形码扫描数据。 PC卡接口的一些实施例对未编码的条形码扫描信号进行采样，并通过PCMCIA总线将样本传送到主机，以便通过适当编程的主机进行解码。

公开(公告)号：US5613074A

公开(公告)日：1997-03-18

申请号：US366510

申请日：1994-12-30

Applicant: William C. Galloway

Inventor： William C. Galloway

IPC: G06F13/40 ,  H01J13/00

CPC classification number: G06F13/4072

Abstract: A system for detecting the presence and size of a SCSI device on a SCSI bus and terminating the SCSI bus accordingly. A SCSI controller is capable of driving two branches of a SCSI bus, each branch having a different data size. When the SCSI controller is at the end of a SCSI chain, termination is enabled, otherwise termination is disabled. Termination is performed on the portions of the SCSI data bus requiring termination based on the presence and size of SCSI devices on the branches used.

Abstract translation: 用于检测SCSI总线上的SCSI设备的存在和大小并相应地终止SCSI总线的系统。 SCSI控制器能够驱动SCSI总线的两个分支，每个分支具有不同的数据大小。 当SCSI控制器处于SCSI链的末尾时，终止启用，否则终止被禁用。 基于所使用的分支上的SCSI设备的存在和大小，在需要终止的SCSI数据总线的部分上执行终止。

公开(公告)号：US5596721A

公开(公告)日：1997-01-21

申请号：US760072

申请日：1991-09-13

Applicant: Ichiro Masse ,  Takanori Miyamoto ,  Takashi Morita ,  Toshiro Suzuki ,  Eiichi Amada

Inventor： Ichiro Masse ,  Takanori Miyamoto ,  Takashi Morita ,  Toshiro Suzuki ,  Eiichi Amada

IPC: G06F13/00 ,  G06F3/14 ,  H04M11/00 ,  H01J13/00

CPC classification number: G06F3/1454

Abstract: A screen communication method and system for communicating screen data between a plurality of interconnected terminal units each having a display part and an input part, wherein each time screen modifying data is input from the display part, each of the terminal units transmits a modifying right request to another terminal unit before transmitting the screen modifying data, and obtains a modifying right under such a condition that each terminal unit receives no screen modifying request from another terminal unit within a predetermined period of time after the transmission of the first modifying right request.

Abstract translation: 一种屏幕通信方法和系统，用于在具有显示部分和输入部分的多个互连的终端单元之间传送屏幕数据，其中每个时间屏幕修改数据从显示部分输入，每个终端单元发送修改权限请求 在发送画面修改数据之前到另一个终端单元，并且在每个终端单元在发送第一修改权请求之后的预定时间段内不从另一个终端单元接收到屏幕修改请求的条件下获得修改权限。

公开(公告)号：US5594873A

公开(公告)日：1997-01-14

申请号：US353047

申请日：1994-12-08

Applicant: James E. Garrett

Inventor： James E. Garrett

IPC: G06F9/445 ,  H01J13/00

CPC classification number: G06F9/4411

Abstract: A method and apparatus for identifying option modules or expansion devices coupled to an expansion bus using time domain methods. According to the present invention, each expansion device includes logic circuitry that asserts an identification signal a preset time duration after a host reset signal is pulsed. A unique preset time duration or time constant is designated for each expansion device, and the host computer identifies each expansion device by the length or duration of the identification signal. In the preferred embodiment, during the power-on sequence the computer system asserts a reset signal pulse to the identification logic in each respective expansion device which directs the expansion device to assert its identifying signal. The host computer determines the length of time between assertion of the reset signal pulse and assertion of the identification signal and uses this information to determine the type of expansion device.

Abstract translation: 一种用于识别使用时域方法耦合到扩展总线的选项模块或扩展设备的方法和装置。 根据本发明，每个扩展装置包括逻辑电路，其在主机复位信号被脉冲之后断言识别信号预设的持续时间。 为每个扩展设备指定唯一的预设持续时间或时间常数，并且主计算机根据识别信号的长度或持续时间来识别每个扩展设备。 在优选实施例中，在上电序列期间，计算机系统向每个相应的扩展装置中的识别逻辑断言复位信号脉冲，其指导扩展装置断言其识别信号。 主计算机确定重置信号脉冲的断言和识别信号的断言之间的时间长度，并使用该信息来确定扩展设备的类型。