Method and system of high-availability PCIE SSD with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset

    公开(公告)号:US09965356B2

    公开(公告)日:2018-05-08

    申请号:US15256350

    申请日:2016-09-02

    Inventor: Shu Li

    CPC classification number: G06F11/142 G06F2201/805 G06F2201/85

    Abstract: It is detected that an error has occurred on an FPGA while the FPGA is operating in a first mode, wherein the error is not correctable by the FPGA itself. The FPGA is configurable to operate in the first mode in which a set of processing steps is to be performed by a first set of logic cells within the FPGA, or in a second mode in which at least a portion of the set of processing steps is to be performed outside the FPGA enabled by a second set of logic cells within the FPGA. An error location associated with the error is identified. In the event that the error location is deemed to have occurred in a critical subset of the first set of logic cells: the FPGA is switched to operate in the second mode; at least one of the first set of logic cells is reconfigured; and upon successful reconfiguration, the FPGA is switched to operate in the first mode.

    Node, arithmetic processing device, and arithmetic processing method

    公开(公告)号:US09959173B2

    公开(公告)日:2018-05-01

    申请号:US15172212

    申请日:2016-06-03

    Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Patent Agency Ranking