Abstract:
A method is presented for using a hard disk drive which contains a non-volatile random access memory (NVRAM) and a computer-usable disk medium. A usage value is maintained for the number of accesses to the computer-usable disk medium, and the usage value is stored within the NVRAM. In a system that is connected to multiple hard disk drives, the usage values for the hard disk drives can be compared to determine a youngest disk drive or a lowest amount of usage amongst the multiple hard disk drives. When data needs to be mirrored or backed-up to one of the hard disk drives, it can be copied to the youngest or least-used hard disk drive. If an operating system installation needs to be performed, the operating system files can be stored on the youngest or least-used hard disk drive.
Abstract:
A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
Abstract:
A utilization analyzer acquires accumulator values from multiple accumulators. Each accumulator corresponds to a particular processor thread and also corresponds to a particular processor utilization resource register (PURR). The utilization analyzer identifies, from the multiple accumulators, a combination of equal accumulators that each includes a largest accumulator value. Next, the utilization analyzer selects a subset of processor utilization resource registers from a combination of processor utilization resource registers that correspond to the combination of equal accumulators. The subset of processor utilization resource registers omits at least one processor utilization resource register from the combination of utilization resource registers. In turn, the utilization analyzer increments each of the subset of utilization resource registers.
Abstract:
Provides control of the workload, flow control, and concurrency control of a computer system through the use of only external performance monitors. Data collected by external performance monitors are used to build a simple, black box model of the computer system, comprising two resources: a virtual bottleneck resource and a delay resource representing all non-bottleneck resources combined. The service times of the two resource types are two parameters of the black box model. The two parameters are evaluated based on historical data collected by the external performance monitors. The workload capacity that avoids saturation of the bottleneck resource is then determined and used as a control variable by a flow controller to limit the workload on the computer system. The workload may include a mix of traffic classes. In such a case, data is collected, parameters are evaluated and control variables are determined for each of the traffic classes.
Abstract:
Methods and systems for measuring available direct memory access (DMA) throughput are disclosed, including providing a plurality of DMA channels, the DMA channels comprising a measuring DMA channel and other DMA channels, the measuring DMA channel having a lowest data rate priority, and determining an available DMA throughput by measuring a current data rate at which the measuring DMA channel is serviced in response to initiating a data transfer on the measuring DMA channel.
Abstract:
An indication of a start of an execution of a process can be received, and a time counter associated with measuring a time elapsed can be initiated by the execution of the process. The time elapsed by the execution of the process can be compared with a predetermined threshold timeout value, and a report indicating the time elapsed by the execution of the process and whether the elapsed time exceeded the predetermined threshold timeout value can be automatically generated.
Abstract:
An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.
Abstract:
Embodiments include a reference counting system and method for a multiprocessor system including distributed per-CPU counters having a dynamically variable batch size. A global counter is dynamically updated as each per-CPU counter reaches its associated batch size. An initial batch size provides a desired scalability. The batch size is automatically reduced as the global count approaches a predefined target, to increase the accuracy of the global count. Counting can be performed atomically using architecturally supported atomic operations. Using synchronized counters, counting can be done with a lock held by each processor to provide the necessary mutual exclusion for performing the atomic operations.
Abstract:
A computer configuration utility automatically alters system configuration parameters to sample multiple different configurations. At least one workrate metric is measured at each sampled configuration. The workrate measurements for the multiple different configurations are compared to determine the effect of different configurations with respect to at least one optimization criterion. System configuration is automatically adjusted to the optimum configuration. Preferably, the workrate metric is (non-idle) instructions executed per unit of time.
Abstract:
Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.