公开(公告)号：US20140198597A1

公开(公告)日：2014-07-17

申请号：US14156792

申请日：2014-01-16

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/404 ,  G11C11/40611 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50016 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/104 ,  G11C2211/4062

Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.

Abstract translation: 集成电路可以包括数字逻辑电路，存储器刷新电路，第一个一个或多个动态随机存取存储器（DRAM）单元和第二个一个或多个DRAM单元。 第一DRAM单元可以被存储器刷新电路刷新，而第二DRAM单元不被任何存储器刷新电路刷新。 第一DRAM单元和第二DRAM单元中的每一个可以是单晶体管单元。 第一DRAM单元可用于存储以小于阈值频率覆盖的数据。 第二DRAM单元可用于存储以大于阈值频率覆盖的数据。 可以在集成电路的运行时间期间调整第一DRAM单元刷新的速率。

公开(公告)号：US20140173640A1

公开(公告)日：2014-06-19

申请号：US14187191

申请日：2014-02-21

Applicant: MaxLinear, Inc.

Inventor： Brendan WALSH ,  Curtis Ling

IPC: H04N21/2543 ,  H04N21/81

CPC classification number: H04N21/25435 ,  G06Q30/02 ,  G06Q30/0201 ,  G06Q30/0241 ,  G06Q30/0264 ,  G06Q30/0273 ,  G06Q50/188 ,  H04N21/812

Abstract: A method for targeted advertisement includes storing a profile tag associated with each user in a device maintained by that user. Each profile tag includes the demographic information of its associated user. A multitude of target tags are also transmitted to the users. Each target tag is associated with an advertiser and includes the demographic information of the users. The advertisements and their corresponding target tags are transmitted and cached in the devices maintained by the users. The number of matches between the target tags and the user profiles are supplied to their respective advertisers. The advertisers use the matching number to modify the prices they are willing to offer for the commercial break. The target tags include information that is used to select one of the cached advertisement for playing during the commercial break.

Abstract translation: 一种用于目标广告的方法包括将与每个用户相关联的简档标签存储在由该用户维护的设备中。 每个配置文件标签包括其关联用户的人口统计信息。 许多目标标签也传送给用户。 每个目标标签与广告客户相关联，并包括用户的人口统计信息。 广告及其相应的目标标签被传送和缓存在由用户维护的设备中。 目标标签和用户资料之间的匹配数量被提供给其各自的广告商。 广告客户使用匹配号码修改他们愿意为商业休息提供的价格。 目标标签包括用于选择在商业中断期间播放的缓存广告之一的信息。

公开(公告)号：US20140064420A1

公开(公告)日：2014-03-06

申请号：US14012772

申请日：2013-08-28

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Timothy Gallagher ,  Sridhar Ramesh

IPC: H04L7/00

CPC classification number: H04L7/00 ,  H04J3/0697 ,  H04L7/0083 ,  H04L12/2801 ,  H04L12/40136 ,  Y02D50/10

Abstract: A network device may comprise one or more circuits including a clock signal generator, an ADC, and a processor. The ADC may digitize a received signal across a range of frequencies that encompasses a first band of frequencies used for a first network and a second band of frequencies used for a second network. A sampling frequency of the ADC may be determined by a frequency of a clock signal output by the clock signal generator. The processor may determine whether the first network is active and whether the second network is active. The processor may configure the clock generator such that, when both of the first network and the second network are active, the clock signal is set to a first frequency, and when the first network is active and the second network is inactive, the clock signal is set to a second frequency.

Abstract translation: 网络设备可以包括一个或多个电路，包括时钟信号发生器，ADC和处理器。 ADC可以在包含用于第一网络的第一频带和用于第二网络的第二频带的频率范围内对接收到的信号进行数字化。 ADC的采样频率可以由时钟信号发生器输出的时钟信号的频率来确定。 处理器可以确定第一网络是否是活动的以及第二网络是否是活动的。 处理器可以配置时钟发生器，使得当第一网络和第二网络都处于活动状态时，时钟信号被设置为第一频率，并且当第一网络有效并且第二网络不活动时，时钟信号 被设置为第二频率。

公开(公告)号：US12235381B2

公开(公告)日：2025-02-25

申请号：US18172282

申请日：2023-02-21

Applicant: MAXLINEAR, INC.

Inventor： Curtis Ling

IPC: G01S7/03 ,  G01S13/931

Abstract: A system comprises a first phased array radar assembly configured to be attached to a vehicle. The first phased array radar assembly includes a first plurality of antennas arranged in an array and attached to a circuit board. The system also includes one or more circuits attached to the circuit board. Each of the one or more circuits includes transmitter circuitry communicatively coupled to a subset of the first plurality of antennas and receiver circuitry communicatively coupled to the subset of the first plurality of antennas.

公开(公告)号：US20240356445A1

公开(公告)日：2024-10-24

申请号：US18762569

申请日：2024-07-02

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Shantha Murthy Prem Swaroop ,  Vinit Jayaraj

IPC: H02M3/158 ,  H02M3/156 ,  H03M1/14

CPC classification number: H02M3/1584 ,  H02M3/156 ,  H02M3/1586 ,  H03M1/143

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.

公开(公告)号：US20230280445A1

公开(公告)日：2023-09-07

申请号：US18172282

申请日：2023-02-21

Applicant: MAXLINEAR, INC.

Inventor： Curtis Ling

IPC: G01S7/03 ,  G01S13/931

CPC classification number: G01S7/032 ,  G01S13/931

Abstract: A system comprises a first phased array radar assembly configured to be attached to a vehicle. The first phased array radar assembly includes a first plurality of antennas arranged in an array and attached to a circuit board. The system also includes one or more circuits attached to the circuit board. Each of the one or more circuits includes transmitter circuitry communicatively coupled to a subset of the first plurality of antennas and receiver circuitry communicatively coupled to the subset of the first plurality of antennas.

公开(公告)号：US11567168B2

公开(公告)日：2023-01-31

申请号：US16372595

申请日：2019-04-02

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling

IPC: G01S7/282 ,  G01S7/41

Abstract: A radar system comprises a transmitter and a receiver. The radar system is operable to define a near range and a far range. The radar system is operable to, during each one of a plurality of time intervals, repeatedly transmit, via the transmitter, a plurality of OFDM symbols. The transmitter is operable to select a transmit power for the transmission during the one of the time intervals based on from which of the near range and the far range reflections of the OFDM symbols are to be received during the one of the time intervals. The receiver is operable to receive reflections of the OFDM symbols, and process, in the receiver, the reflections of the OFDM symbols to detect objects within the near range and the far range.

公开(公告)号：US11044704B2

公开(公告)日：2021-06-22

申请号：US15964580

申请日：2018-04-27

Applicant: Maxlinear, Inc.

Inventor： Timothy Gallagher ,  Curtis Ling ,  Alan Trerise ,  Kishore Seendripu

IPC: H04W4/00 ,  H04W72/04 ,  H04W16/02 ,  H04W84/12 ,  H04W88/08

Abstract: A WiFi access point (AP) includes a receive radio frequency (RF) front end and a baseband processor that controls operation of the receive RF front end. The RF front end captures signals over a wide spectrum that includes a plurality of WiFi frequency bands (2.4 GHz and 5 GHz) and channelizes one or more WiFi channels from the captured signals. The baseband processor combines a plurality of blocks of WiFi channels to create one or more aggregated WiFi channels. The receive RF front end may be integrated on a first integrated circuit and the baseband processor may be integrated on a second integrated circuit. The first and second integrated circuits may be integrated on a single package. The RF front end and the baseband processor may be integrated on a single integrated circuit. The WiFi access point comprises a routing module that is communicatively coupled to the baseband processor.

公开(公告)号：US10910710B2

公开(公告)日：2021-02-02

申请号：US16194320

申请日：2018-11-17

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Sridhar Ramesh

IPC: H01Q3/40 ,  H01Q3/26 ,  H01Q21/00 ,  H01Q3/42 ,  H01Q21/06

Abstract: Systems and methods are provided for distortion redirection in phased arrays. In an electronic device configured for transmission and reception of signals and having a two-dimensional phased array, effects of distortion, corresponding to at least one processing function applied during communication of signals, on the communication of signals may be assessed, and based on the effects of distortion, one or more adjustments for mitigating the effects of distortion may be configured and applied during processing of signals. Assessing the effects of distortion may include determining one or more characteristics associated with the communication of the signals, where the one or more characteristics relate and/or are subject to the effects of the distortion, and assessing the effects of distortion based on the one or more characteristics.

公开(公告)号：US10763957B2

公开(公告)日：2020-09-01

申请号：US16659170

申请日：2019-10-21

Applicant: MaxLinear, Inc.

Inventor： Steven J. Krapp ,  Sridhar Ramesh ,  Curtis Ling ,  Leonard Dauphinee ,  Kenneth S. Walley

IPC: H04B10/00 ,  H04B10/038 ,  H04B10/25 ,  H04J14/00

Abstract: Systems and methods are provided for supporting redundancy and outage resolution in coaxial networks with ideal taps.