Signal receiving circuit adapted for multiple digital video/audio transmission interface standards
    21.
    发明授权
    Signal receiving circuit adapted for multiple digital video/audio transmission interface standards 有权
    信号接收电路适用于多个数字视频/音频传输接口标准

    公开(公告)号:US07945706B2

    公开(公告)日:2011-05-17

    申请号:US12128634

    申请日:2008-05-29

    Abstract: The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

    Abstract translation: 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子,一组第一分离输入端子,用于接收与该组共享输入端子对应的第一传输规格的输入信号,以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路,以及耦合到输入接口和控制电路的处理模块,用于根据控制信号处理输入信号以产生输出信号。

    CHANNEL CONDITION DEPENDENT SCHEDULING
    22.
    发明申请
    CHANNEL CONDITION DEPENDENT SCHEDULING 有权
    频道条件依赖调度

    公开(公告)号:US20110085512A1

    公开(公告)日:2011-04-14

    申请号:US12997096

    申请日:2008-06-26

    Applicant: Bo Lin Wim Rouwet

    Inventor: Bo Lin Wim Rouwet

    CPC classification number: H04W4/20

    Abstract: An apparatus for data traffic scheduling comprises a scheduler assigning at least one priority parameter value prioritising usage of a communication resource comprising a plurality of logical channels, to each of a plurality of users of the communication resource, a channel analyser providing at least one channel condition indicator for each logical channel, and a filter providing a scheduling parameter value for each logical channel to the scheduler determining the priority parameter value, the scheduling parameter value being a weighted average of a plurality of values of the at least one channel condition indicator.

    Abstract translation: 一种用于数据业务调度的装置包括调度器,其向通信资源的多个用户中的每一个分配分配包括多个逻辑信道的通信资源的使用优先权的至少一个优先级参数值,信道分析器提供至少一个信道条件 指示符,以及向确定优先级参数值的调度器提供每个逻辑信道的调度参数值的过滤器,调度参数值是至少一个信道条件指示符的多个值的加权平均值。

    METERING PUMP AND DRIVE DEVICE THEREOF
    24.
    发明申请
    METERING PUMP AND DRIVE DEVICE THEREOF 有权
    计量泵及其驱动装置

    公开(公告)号:US20100303656A1

    公开(公告)日:2010-12-02

    申请号:US12854193

    申请日:2010-08-11

    Applicant: Bo LIN Jiang LIN

    Inventor: Bo LIN Jiang LIN

    CPC classification number: F04B13/00 F04B7/04 F04B35/01

    Abstract: A drive device, comprising a housing, a rod, a limiting device, a sliding block, a rotating block, a pair of springs, a pair of first grooves, and a second groove. The rod passes through the sliding block, an axis is disposed on the sliding block, the rotating block is disposed on the axis, the springs are disposed on both sides of the rotating block, the top of the spring is contacted with one side of the rotating block, the first grooves are disposed on one side of the rod opposite to the housing, the second groove is disposed on inner side of the housing opposite to the first groove, a middle part of the second groove is lower than other parts thereof, one end of the rotating block slides in the second groove, and the other end of the rotating block slides in and between the first grooves.

    Abstract translation: 一种驱动装置,包括壳体,杆,限制装置,滑动块,旋转块,一对弹簧,一对第一凹槽和第二凹槽。 杆穿过滑动块,轴线设置在滑动块上,旋转块设置在轴上,弹簧设置在旋转块的两侧,弹簧的顶部与 所述第一凹槽设置在与所述壳体相对的所述杆的一侧上,所述第二凹槽设置在所述壳体的与所述第一凹槽相对的内侧上,所述第二凹槽的中间部分比其它部分低, 旋转块的一端在第二槽中滑动,并且旋转块的另一端在第一槽之间滑动。

    DIFFERENTIAL SIGNAL GENERATING DEVICE
    25.
    发明申请
    DIFFERENTIAL SIGNAL GENERATING DEVICE 有权
    差分信号发生器

    公开(公告)号:US20100238159A1

    公开(公告)日:2010-09-23

    申请号:US12726931

    申请日:2010-03-18

    CPC classification number: H03K5/151 H03K19/0008

    Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

    Abstract translation: 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时,控制电路接收源信号并产生对应于第一模式的控制信号,并且当源信号符合第二预定义状态时,控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时,差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时,差分信号驱动器输出非差分信号输出。

    DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT
    26.
    发明申请
    DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT 有权
    用于控制框架输入和输出的装置和方法

    公开(公告)号:US20100188574A1

    公开(公告)日:2010-07-29

    申请号:US12692389

    申请日:2010-01-22

    CPC classification number: H04N7/0105 H04N7/0132

    Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

    Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备,该设备包括缓冲器,缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号,并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据,并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

    PACKET PROCESSING SYSTEM AND RELATED PACKET PROCESSING METHOD
    30.
    发明申请
    PACKET PROCESSING SYSTEM AND RELATED PACKET PROCESSING METHOD 审中-公开
    分组处理系统及相关分组处理方法

    公开(公告)号:US20070201475A1

    公开(公告)日:2007-08-30

    申请号:US11674154

    申请日:2007-02-13

    Abstract: A packet processing system includes: a receiver for receiving a previous packet and a current packet through an interface; a storage device for storing the previous packet; a comparing module, coupled to the storage device and the receiver, for comparing contents of the current packet with contents of the previous packet to generate a comparison result; and a packet reading module, coupled to the storage device, for reading the contents of the current packet according to the comparison result.

    Abstract translation: 分组处理系统包括:接收器,用于通过接口接收先前分组和当前分组; 用于存储先前分组的存储设备; 耦合到存储设备和接收器的比较模块,用于将当前分组的内容与先前分组的内容进行比较以产生比较结果; 以及分组读取模块,耦合到存储设备,用于根据比较结果读取当前分组的内容。

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