公开(公告)号：US08889567B2

公开(公告)日：2014-11-18

申请号：US13234946

申请日：2011-09-16

Applicant: Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Hui-Chun Yang

Inventor： Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Hui-Chun Yang

IPC: H01L21/316 ,  H01L21/3105 ,  C23C16/56 ,  C23C16/52 ,  H01L21/02 ,  C23C16/40 ,  H01L21/768

CPC classification number: H01L23/5329 ,  C23C16/401 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/7682 ,  H01L23/562 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.

Abstract translation: 多孔SiCOH的低k电介质层的方法和装置。 一种方法包括将半导体衬底放置在气相沉积室中; 将反应性气体引入气相沉积室以形成包含SiCOH和可分解致孔剂的电介质膜; 沉积介电膜以使Si-CH3与SiO网络键的比例小于或等于0.25; 并进行固化固化时间以从电介质膜基本上除去所有致孔剂。 在一个实施方案中，致孔剂包含环状烃。 造孔剂可以是UV固化的。 在实施例中，公开了用于沉积电介质膜的不同降低的Si-CH 3与SiO网络比。 公开了一种包括低k电介质层的半导体器件的装置。

公开(公告)号：US08629056B2

公开(公告)日：2014-01-14

申请号：US13107549

申请日：2011-05-13

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC: H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

Abstract translation: 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US20130277853A1

公开(公告)日：2013-10-24

申请号：US13452446

申请日：2012-04-20

Applicant: Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

Inventor： Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Abstract translation: 公开了半导体器件，其制造方法以及形成其导电特征的方法。 半导体器件包括设置在工件上方的绝缘材料层。 绝缘材料层包括含有约13％或更多碳（C）的含硅材料。 导电特征设置在绝缘材料层内。 导电特征包括设置在其顶表面上的覆盖层。

公开(公告)号：US20090258487A1

公开(公告)日：2009-10-15

申请号：US12102695

申请日：2008-04-14

Applicant: Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

Inventor： Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

IPC: H01L21/4763

CPC classification number: H01L21/76825 ,  H01L21/3105

Abstract: A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer.

Abstract translation: 一种用于形成集成电路结构的方法包括提供半导体衬底; 在半导体衬底上形成低k电介质层; 使用远程等离子体法产生氢自由基; 使用氢自由基对低k电介质层进行第一次氢自由基处理; 在低k电介质层中形成开口; 用导电材料填充开口; 并执行平面化以去除低k电介质层上的过量导电材料。

公开(公告)号：US20090166817A1

公开(公告)日：2009-07-02

申请号：US11968324

申请日：2008-01-02

Applicant: Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

Inventor： Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

IPC: H01L23/58

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

Abstract translation: 用于高级互连的极低k（ELK）电介质膜方案包括上ELK电介质层和具有不同折射率的下ELK电介质。 上部ELK介电层的折射率大于下部ELK介电层的折射率。

公开(公告)号：US07485949B2

公开(公告)日：2009-02-03

申请号：US11797310

申请日：2007-05-02

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/58

CPC classification number: H01L23/53295 ,  H01L21/563 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

Abstract translation: 公开了一种半导体器件。 该器件包括衬底，第一多孔SiCOH电介质层，第二多孔SiCOH电介质层和氧化物层。 第一多孔SiCOH介电层覆盖在基底上。 第二多孔SiCOH介电层覆盖第一多孔SiCOH介电层。 氧化物层覆盖第二多孔SiCOH介电层。 第二多孔SiCOH介电层中的碳的原子百分比在第一多孔SiCOH介电层中的原子百分比为16％至22％。

公开(公告)号：US20080311756A1

公开(公告)日：2008-12-18

申请号：US11764053

申请日：2007-06-15

Applicant: Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

Inventor： Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

IPC: H01L21/311

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31138

Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Abstract translation: 提供了一种通过降低RC延迟时间来提高集成电路性能的系统和方法。 优选的实施方案包括在低k电介质蚀刻之后向灰/冲击等离子体工艺中添加反应性蚀刻气体。 说明性实施例实现了在低k电介质蚀刻期间形成的损伤层的去除。

公开(公告)号：US07456093B2

公开(公告)日：2008-11-25

申请号：US10884719

申请日：2004-07-03

Applicant: Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

Inventor： Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/53295 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/3135 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.

Abstract translation: 具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

公开(公告)号：US20080171431A1

公开(公告)日：2008-07-17

申请号：US11654427

申请日：2007-01-17

Applicant: Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

Inventor： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract translation: 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

公开(公告)号：US20080061442A1

公开(公告)日：2008-03-13

申请号：US11531304

申请日：2006-09-13

Applicant: Chung-Chi Ko ,  Keng-Chu Lin ,  Chia-Cheng Chou

Inventor： Chung-Chi Ko ,  Keng-Chu Lin ,  Chia-Cheng Chou

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/02203 ,  H01L21/3121 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and-the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings

Abstract translation: 提供互连结构。 互连结构的示例性实施例包括其上具有低k电介质层的衬底。 通孔开口和沟槽开口形成在低k电介质层中，其中沟槽开口形成在通孔开口上方，并且通孔开口暴露衬底的一部分。 衬底层形成在由槽沟露出的低k电介质层的侧壁上，并且通过沟槽和由沟槽通孔部分露出的底表面，其中低k电介质层的侧壁上的衬垫层的部分暴露于 形成在由沟槽部分露出的底表面上的沟槽和通孔保护层以及衬垫层的部分包括不同的材料。 在沟槽和通孔开口中形成共形导电阻挡层，覆盖衬垫层和衬底的暴露部分。 在导电阻挡层上形成导电层，填充沟槽和通孔